Inventor

LEE HYUN YOO

US50 patents

⚠️ This page may combine multiple inventors who share the name “LEE HYUN YOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE HYUN YOO

MICRON TECHNOLOGY INC

Apparatuses and methods for duty cycle error correction of clock signals

Apparatuses and methods for duty cycle distortion correction of clocks

Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal

Apparatuses and methods for duty cycle error correction of clock signals

Apparatuses and methods for providing active and inactive clock signals

Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal

Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories

Automated error correction with memory refresh

Shared error correction code (ECC) circuitry

Adaptive memory registers

Multi-rail power transition

Equalization for pulse-amplitude modulation

Interactive memory self-refresh control

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal

Source follower-based sensing scheme

Apparatuses and methods including memory commands for semiconductor memories

Systems and methods for improving signal margin for input buffer circuits

Apparatuses and methods for duty cycle distortion correction of clocks

Apparatuses and methods for input signal receiver circuits

Apparatuses and methods for configurable command and data input circuits for semiconductor memories

Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories

Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories

Bus training with interconnected dice

Adaptive selection of a configuration-dependent operand

Automated error correction with memory refresh

Adaptive memory refresh control

Apparatus with combinational access mechanism and methods for operating the same

Burst mode for self-refresh

Apparatus with combinational access mechanism and methods for operating the same

Apparatuses and methods for configurable command and data input circuits for semiconductor memories

Bank-level self-refresh

Programmable memory timing

Multiple error correction code (ECC) engines and ECC schemes

Programmable memory timing

Semiconductor device performing refresh operation

Source follower-based sensing scheme

Apparatuses and systems for providing power to a memory

Source follower-based sensing scheme

Bank-level self-refresh

Asymmetric read-write sequence for interconnected dies

Bus training with interconnected dice

Write timing compensation

Inter-die refresh control

Apparatuses and methods for providing active and inactive clock signals

Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal

Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same

Apparatuses and methods for configurable command and data input circuits forsemiconductor memories

LODESTAR LICENSING GROUP LLC

Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same

Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same