Inventor

VOGT PETE D

US55 patents

⚠️ This page may combine multiple inventors who share the name “VOGT PETE D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VOGT PETE D

INTEL CORP

Memory channel with unidirectional links

Method and apparatus for utilizing write buffers in memory control/interface

Calibrating data strobe signal using adjustable delays with feedback

Lane testing with variable mapping

Method and apparatus for memory compression

Early CRC delivery for partial frame

Memory channel with hot add/remove

Memory control translators

Memory channel with bit lane fail-over

Data accumulation between data path having redrive circuit and memory device

Memory device identification

Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems

Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding

Memory agent core clock aligned to lane

Memory channel utilizing permuting status patterns

Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal

Training pattern for a biased clock recovery tracking loop

System and method for maintaining memory coherency in a computer system having multiple system buses

Techniques to access or operate a dual in-line memory module via multiple data channels

Extended platform with additional memory module slots per CPU socket

Check codes mapped across multiple frames

Memory modules that receive clock information and are placed in a low power state

Memory channel with unidirectional links

Memory channel with redundant presence detect

Buffered memory module with implicit to explicit memory command expansion

Combined command and data code

Embedded heat spreader

Techniques to access or operate a dual in-line memory module via multiple data channels

Extended platform with additional memory module slots per CPU socket and configured for increased performance

Embedded ECC address mapping

Memory channel with bit lane fail-over

Memory channel with bit lane fail-over

Set partitioning for cache memories

Method, apparatus, and system for memory read transaction biasing in mirrored mode to provide thermal management

Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystems

Remote memory operations

Read delivery for memory subsystem with narrow bandwidth repeater channel

Synchronized memory channels with unidirectional links

I/O data interconnect reuse as repeater

Extended platform with additional memory module slots per CPU socket and configured for increased performance

Extended platform with additional memory module slots per CPU socket

Extended application of error checking and correction code in memory

Memory channel having deskew separate from redrive

Embedded heat spreader

COROLLARY INC

System and method for maintaining memory coherency in a computer system having multiple system buses

System and method for maintaining memory coherency in a computer system having multiple system buses

VOGT PETE D

Memory channel having deskew separate from redrive

Disabling outbound drivers for a last memory buffer on a memory channel

PANIKKAR ADARSH

Training pattern for a biased clock recovery tracking loop

TAHOE RES LTD

Stacked memory with interface providing offset interconnects