Inventor
SAMUDRALA SRIDHAR
US28 patents
⚠️ This page may combine multiple inventors who share the name “SAMUDRALA SRIDHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS9778909B2Oct 3, 2017
Double rounded combined floating-point multiply and add
INTEL CORP7 citations83
US9513917B2Dec 6, 2016
Vector friendly instruction format and execution thereof
INTEL CORP10 citations82
US9477441B2Oct 25, 2016
Double rounded combined floating-point multiply and add
INTEL CORP3 citations72
US12086594B2Sep 10, 2024
Vector friendly instruction format and execution thereof
INTEL CORP0 citations60
US11740904B2Aug 29, 2023
Vector friendly instruction format and execution thereof
INTEL CORP0 citations60
US11210096B2Dec 28, 2021
Vector friendly instruction format and execution thereof
INTEL CORP0 citations60
US12231339B2Feb 18, 2025
Extension of openvswitch megaflow offloads to hardware to address hardware pipeline limitations
INTEL CORP1 citations57
US12170624B2Dec 17, 2024
Technologies that provide policy enforcement for resource access
INTEL CORP0 citations56
US9389871B2Jul 12, 2016
Combined floating point multiplier adder with intermediate rounding logic
INTEL CORP0 citations51
US10795680B2Oct 6, 2020
Vector friendly instruction format and execution thereof
INTEL CORP0 citations50
DIGITAL EQUIPMENT CORP
4 patentsUS5341319AAug 23, 1994
Method and apparatus for controlling a rounding operation in a floating point multiplier circuit
DIGITAL EQUIPMENT CORP25 citations91
US4849923AJul 18, 1989
Apparatus and method for execution of floating point operations
DIGITAL EQUIPMENT CORP37 citations91
US5317527AMay 31, 1994
Leading one/zero bit detector for floating point operation
DIGITAL EQUIPMENT CORP45 citations86
US4852039AJul 25, 1989
Apparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective subtraction procedure
DIGITAL EQUIPMENT CORP8 citations71
HEWLETT PACKARD DEVELOPMENT CO
4 patentsUS6564239B2May 13, 2003
Computer method and apparatus for division and square root operations using signed digit
HEWLETT PACKARD DEVELOPMENT CO18 citations90
US7127483B2Oct 24, 2006
Method and system of a microprocessor subtraction-division floating point divider
HEWLETT PACKARD DEVELOPMENT CO10 citations73
US6779012B2Aug 17, 2004
Computer method and apparatus for division and square root operations using signed digit
HEWLETT PACKARD DEVELOPMENT CO6 citations71
US6732135B1May 4, 2004
Method and apparatus for accumulating partial quotients in a digital processor
HEWLETT PACKARD DEVELOPMENT CO3 citations60
WIEDEMEIER JEFF
3 patentsUS9141386B2Sep 22, 2015
Vector logical reduction operation implemented using swizzling on a semiconductor chip
WIEDEMEIER JEFF10 citations81
US8667042B2Mar 4, 2014
Functional unit for vector integer multiply add instruction
WIEDEMEIER JEFF13 citations81
US9092213B2Jul 28, 2015
Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation
WIEDEMEIER JEFF2 citations60
COMPAQ INFORMATION TECHNOLOGIE
2 patentsUS6366942B1Apr 2, 2002
Method and apparatus for rounding floating point results in a digital processing system
COMPAQ INFORMATION TECHNOLOGIE26 citations89
US6360241B1Mar 19, 2002
Computer method and apparatus for division and square root operations using signed digit
COMPAQ INFORMATION TECHNOLOGIE10 citations71