Inventor

HANAWA MAKOTO

JP35 patents

⚠️ This page may combine multiple inventors who share the name “HANAWA MAKOTO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HANAWA MAKOTO

HITACHI LTD

Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank

Multiprocessor system having distinct data bus and address bus arbiters

Multiprocessor system having a processor invalidating operand cache when lock-accessing

Semiconductor memory device for performing parallel operations on hierarchical data lines

Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction

Data processor having two instruction registers connected in cascade and two instruction decoders

Semiconductor associative memory device with current sensing

Clocked logic gate circuit

Multi-port memory and a data processor accessing the same

Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition

Logic circuit having error detection function and processor including the logic circuit

Instruction branching method and a processor

System with reservation instruction execution to store branch target address for use upon reaching the branch point

Pass transistor type selector circuit and digital logic circuit

RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register

Microprocessor for retrying data transfer

Asynchronous signal synchronizing circuit

Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit

Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable

Content-addressable memory

Clocked logic gate circuit

Data processor

Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses

Pipeline processor with prefetch circuit

Data processor

Purge control for ON-chip cache memory

CMOS static logic circuit

Data processor having logical address memories and purge capabilities

Data processor with on-chip logical addressing and off-chip physical addressing

Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus

Data processor capable of executing an instruction that makes a cache memory ineffective

Clocked logic gate circuit

Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory

HITACHI MICROCUMPUTER ENG

System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus

OKI ELECTRIC IND CO LTD

Method and a device for allowing only a specific kind of hardware to correctly execute software