Inventor
LOH YING T
US6 patents
Patents
6 patentsUS5631485AMay 20, 1997
ESD and hot carrier resistant integrated circuit structure
VLSI TECHNOLOGY INC46 citations95
US5496751AMar 5, 1996
Method of forming an ESD and hot carrier resistant integrated circuit structure
VLSI TECHNOLOGY INC48 citations95
US5411906AMay 2, 1995
Method of fabricating auxiliary gate lightly doped drain (AGLDD) structure with dielectric sidewalls
VLSI TECHNOLOGY INC25 citations92
US5340761AAug 23, 1994
Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure
VLSI TECHNOLOGY INC23 citations91
US5196357AMar 23, 1993
Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor
VLSI TECHNOLOGY INC34 citations91
US5227320AJul 13, 1993
Method for producing gate overlapped lightly doped drain (goldd) structure for submicron transistor
VLSI TECHNOLOGY INC20 citations78