Inventor

JANG HYUN-SOON

KR38 patents

⚠️ This page may combine multiple inventors who share the name “JANG HYUN-SOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JANG HYUN-SOON

SAMSUNG ELECTRONICS CO LTD

System and method for performing partial array self-refresh operation in a semiconductor memory device

System and method for performing partial array self-refresh operation in a semiconductor memory device

Integrated circuit memory devices having reduced power consumption requirements during standby mode operation

Power down voltage control method and apparatus

System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle

Semiconductor memory having a plurality of I/O buses

Multi-bank dynamic random access memory devices having all bank precharge capability

Circuit in a semiconductor memory for programming operation modes of the memory

Synchronous dram having a plurality of latency modes

Semiconductor memory

Synchronous semiconductor memory device with a write latency control function

Bit line sensing circuit of a semiconductor memory device

Multi-chip package for reducing parasitic load of pin

System and method for performing partial array self-refresh operation in a semiconductor memory device

Power down voltage control method and apparatus

Sense amplifier of semiconductor integrated circuit

Pad signal detecting circuit in a semiconductor device for detecting a reference voltage in a high-speed interface

Data output buffer of a semiconducter memory device

Semiconductor memory device having a structure for driving input/output lines at a high speed

Data input buffer circuit for use in a semiconductor memory device

Row redundancy circuit for a semiconductor memory device

Semiconductor memory device including post package repair control circuit and post package repair method

Semiconductor memory device

Parallel bit test apparatus and parallel bit test method capable of reducing test time

Multi-chip package for reducing parasitic load of pin

Semiconductor memory device and voltage generating method thereof

Sense amplifier of semiconductor integrated circuit

Internal power supply voltage generating circuit of semiconductor memory device

Programmable refresh circuits and methods for integrated circuit memory devices

Input protection device for improving of delay time on input stage in semi-conductor devices

Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method

Memory using packet controller and memory

Layout structure of fuse bank of semiconductor memory device

Multi-chip package for reducing parasitic load of pin

Semiconductor device with bus line loading compensation circuit

Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines

KIM HONG-BEOM

Method of testing a semiconductor memory device

KIM KAB YONG

Semiconductor device having a plurality of pads