Inventor

EFLAND TAYLOR R

US63 patents

Patents

50 patents

US7268045B2Sep 11, 2007

Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect

TEXAS INSTRUMENTS INC90 citations97

US6531355B2Mar 11, 2003

LDMOS device with self-aligned RESURF region and method of fabrication

TEXAS INSTRUMENTS INC63 citations96

US6395593B1May 28, 2002

Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration

TEXAS INSTRUMENTS INC72 citations96

US6160290ADec 12, 2000

Reduced surface field device having an extended field plate and method for forming the same

TEXAS INSTRUMENTS INC49 citations96

US5406110AApr 11, 1995

Resurf lateral double diffused insulated gate field effect transistor

TEXAS INSTRUMENTS INC58 citations96

US5346835ASep 13, 1994

Triple diffused lateral resurf insulated gate field effect transistor compatible with process and method

TEXAS INSTRUMENTS INC97 citations96

US5306652AApr 26, 1994

Lateral double diffused insulated gate field effect transistor fabrication process

TEXAS INSTRUMENTS INC67 citations96

US6211552B1Apr 3, 2001

Resurf LDMOS device with deep drain region

TEXAS INSTRUMENTS INC122 citations95

US5859456AJan 12, 1999

Multiple transistor integrated circuit with thick copper interconnect

TEXAS INSTRUMENTS INC84 citations95

US7060607B2Jun 13, 2006

Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface

TEXAS INSTRUMENTS INC17 citations93

US6597065B1Jul 22, 2003

Thermally enhanced semiconductor chip having integrated bonds over active circuits

TEXAS INSTRUMENTS INC32 citations93

US6468837B1Oct 22, 2002

Reduced surface field device having an extended field plate and method for forming the same

TEXAS INSTRUMENTS INC28 citations93

US6225673B1May 1, 2001

Integrated circuit which minimizes parasitic action in a switching transistor pair

TEXAS INSTRUMENTS INC34 citations93

US5869882AFeb 9, 1999

Zener diode structure with high reverse breakdown voltage

TEXAS INSTRUMENTS INC41 citations93

US5182222AJan 26, 1993

Process for manufacturing a DMOS transistor

TEXAS INSTRUMENTS INC31 citations93

US7238986B2Jul 3, 2007

Robust DEMOS transistors and method for making the same

TEXAS INSTRUMENTS INC24 citations92

US7135759B2Nov 14, 2006

Individualized low parasitic power distribution lines deposited over active integrated circuits

TEXAS INSTRUMENTS INC21 citations92

US6873021B1Mar 29, 2005

MOS transistors having higher drain current without reduced breakdown voltage

TEXAS INSTRUMENTS INC26 citations92

US6753575B2Jun 22, 2004

Tank-isolated-drain-extended power device

TEXAS INSTRUMENTS INC20 citations92

US6729886B2May 4, 2004

Method of fabricating a drain isolated LDMOS device

TEXAS INSTRUMENTS INC34 citations92

US6680226B2Jan 20, 2004

Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology

TEXAS INSTRUMENTS INC15 citations92

US6483149B1Nov 19, 2002

LDMOS device with self-aligned resurf region and method of fabrication

TEXAS INSTRUMENTS INC47 citations92

US6468849B1Oct 22, 2002

Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology

TEXAS INSTRUMENTS INC24 citations92

US6413824B1Jul 2, 2002

Method to partially or completely suppress pocket implant in selective circuit elements with no additional mask in a cmos flow where separate masking steps are used for the drain extension implants for the low voltage and high voltage transistors

TEXAS INSTRUMENTS INC21 citations92

US6372586B1Apr 16, 2002

Method for LDMOS transistor with thick copper interconnect

TEXAS INSTRUMENTS INC52 citations92

US6150722ANov 21, 2000

Ldmos transistor with thick copper interconnect

TEXAS INSTRUMENTS INC30 citations92

US6147526ANov 14, 2000

Ripple regulator with improved initial accuracy and noise immunity

TEXAS INSTRUMENTS INC30 citations92

US6140702AOct 31, 2000

Plastic encapsulation for integrated circuits having plated copper top surface level interconnect

TEXAS INSTRUMENTS INC28 citations92

US5812006ASep 22, 1998

Optimized power output clamping structure

TEXAS INSTRUMENTS INC30 citations92

US5801091ASep 1, 1998

Method for current ballasting and busing over active device area using a multi-level conductor process

TEXAS INSTRUMENTS INC29 citations92

US5744843AApr 28, 1998

CMOS power device and method of construction and layout

TEXAS INSTRUMENTS INC48 citations92

US5736766AApr 7, 1998

Medium voltage LDMOS device and method of fabrication

TEXAS INSTRUMENTS INC51 citations92

US5728594AMar 17, 1998

Method of making a multiple transistor integrated circuit with thick copper interconnect

TEXAS INSTRUMENTS INC43 citations92

US5119162AJun 2, 1992

Integrated power DMOS circuit with protection diode

TEXAS INSTRUMENTS INC51 citations92

US6160388ADec 12, 2000

Sensing of current in a synchronous-buck power stage

TEXAS INSTRUMENTS INC46 citations91

US6236098B1May 22, 2001

Heat spreader

TEXAS INSTRUMENTS INC29 citations90

US7514329B2Apr 7, 2009

Robust DEMOS transistors and method for making the same

TEXAS INSTRUMENTS INC15 citations84

US7045903B2May 16, 2006

Integrated power circuits with distributed bonding and current flow

TEXAS INSTRUMENTS INC19 citations84

US6784539B2Aug 31, 2004

Thermally enhanced semiconductor chip having integrated bonds over active circuits

TEXAS INSTRUMENTS INC13 citations84

US7195965B2Mar 27, 2007

Premature breakdown in submicron device geometries

TEXAS INSTRUMENTS INC14 citations83

US6784493B2Aug 31, 2004

Line self protecting multiple output power IC architecture

TEXAS INSTRUMENTS INC15 citations83

US6284669B1Sep 4, 2001

Power transistor with silicided gate and contacts

TEXAS INSTRUMENTS INC16 citations82

US6972484B2Dec 6, 2005

Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface

TEXAS INSTRUMENTS INC7 citations74

US6274918B1Aug 14, 2001

Integrated circuit diode, and method for fabricating same

TEXAS INSTRUMENTS INC10 citations74

Showing the top 50 of 63 patents by PatentIndex Score.

EFLAND TAYLOR R

Patents

N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects

N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects

Integrated circuit with bonding layer over active circuitry

Thick plated interconnect and associated auxillary interconnect

ESD protection structure using LDMOS diodes with thick copper interconnect

LDMOS power device with oversized dwell

Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect

LDMOS device with self-aligned RESURF region and method of fabrication

Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration

Reduced surface field device having an extended field plate and method for forming the same

Resurf lateral double diffused insulated gate field effect transistor

Triple diffused lateral resurf insulated gate field effect transistor compatible with process and method

Lateral double diffused insulated gate field effect transistor fabrication process

Resurf LDMOS device with deep drain region

Multiple transistor integrated circuit with thick copper interconnect

Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface

Thermally enhanced semiconductor chip having integrated bonds over active circuits

Reduced surface field device having an extended field plate and method for forming the same

Integrated circuit which minimizes parasitic action in a switching transistor pair

Zener diode structure with high reverse breakdown voltage

Process for manufacturing a DMOS transistor

Robust DEMOS transistors and method for making the same

Individualized low parasitic power distribution lines deposited over active integrated circuits

MOS transistors having higher drain current without reduced breakdown voltage

Tank-isolated-drain-extended power device

Method of fabricating a drain isolated LDMOS device

Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology

LDMOS device with self-aligned resurf region and method of fabrication

Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology

Method to partially or completely suppress pocket implant in selective circuit elements with no additional mask in a cmos flow where separate masking steps are used for the drain extension implants for the low voltage and high voltage transistors

Method for LDMOS transistor with thick copper interconnect

Ldmos transistor with thick copper interconnect

Ripple regulator with improved initial accuracy and noise immunity

Plastic encapsulation for integrated circuits having plated copper top surface level interconnect

Optimized power output clamping structure

Method for current ballasting and busing over active device area using a multi-level conductor process

CMOS power device and method of construction and layout

Medium voltage LDMOS device and method of fabrication

Method of making a multiple transistor integrated circuit with thick copper interconnect

Integrated power DMOS circuit with protection diode

Sensing of current in a synchronous-buck power stage

Heat spreader

Robust DEMOS transistors and method for making the same

Integrated power circuits with distributed bonding and current flow

Thermally enhanced semiconductor chip having integrated bonds over active circuits

Premature breakdown in submicron device geometries

Line self protecting multiple output power IC architecture

Power transistor with silicided gate and contacts

Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface

Integrated circuit diode, and method for fabricating same