Inventor

OULD-AHMED-VALL ELMOUSTAPHA

US461 patents

⚠️ This page may combine multiple inventors who share the name “OULD-AHMED-VALL ELMOUSTAPHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OULD-AHMED-VALL ELMOUSTAPHA

INTEL CORP

Compute unit having independent data paths

Mixed inference using low and high precision

Systems, methods, and apparatuses for dot production operations

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems, methods, and apparatuses for tile diagonal

Systems and methods for performing matrix compress and decompress instructions

Instructions having support for floating point and integer data types in the same register

Coordination and increased utilization of graphics processors during inference

Floating point to fixed point conversion

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Systems and methods for improving cache efficiency and utilization

Sparse optimizations for a matrix accelerator architecture

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Systems, methods, and apparatus for matrix move

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for zeroing a matrix

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for matrix move

Systems, methods, and apparatuses for tile broadcast

Systems, methods, and apparatuses for matrix add, subtract, and multiply

Systems and methods to load a tile register pair

Systems, methods, and apparatus for tile configuration

Systems and methods to zero a tile register pair

Systems and methods for performing instructions specifying ternary tile logic operations

Systems and methods for performing instructions to transform matrices into row-interleaved format

Systems and methods for performing instructions to transpose rectangular tiles

Systems and methods for implementing chained tile operations

Fixed point to floating point conversion

Graphics processor operation scheduling for deterministic latency

Autonomous vehicle advanced sensing and response

Machine learning accelerator mechanism

Compression in machine learning and deep learning processing

Compute optimizations for low precision machine learning operations

Graphics processor data access and sharing

Systems and methods for cache optimization

Apparatuses, methods, and systems for instructions for loading a tile of a matrix operations accelerator

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing nibble-sized operations on matrix elements

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

Systems, methods, and apparatuses for matrix operations

Systems and methods to store a tile register pair to memory

Systems and methods for computing dot products of nibbles in two tile operands

Systems and methods for performing matrix compress and decompress instructions

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems, methods, and apparatuses for dot product operations

OULD-AHMED-VALL ELMOUSTAPHA

Systems, apparatuses, and methods for performing delta decoding on packed data elements