Inventor

VALENTINE ROBERT

IL361 patents

⚠️ This page may combine multiple inventors who share the name “VALENTINE ROBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VALENTINE ROBERT

INTEL CORP

Performance throttling to reduce IC power consumption

Systems, methods, and apparatuses for dot production operations

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems, methods, and apparatuses for tile diagonal

Systems and methods for performing matrix compress and decompress instructions

Floating point to fixed point conversion

Instruction dependency chain indentifier

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Systems, methods, and apparatus for matrix move

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for zeroing a matrix

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for matrix move

Systems, methods, and apparatuses for tile broadcast

Systems, methods, and apparatuses for matrix add, subtract, and multiply

Systems and methods to load a tile register pair

Systems, methods, and apparatus for tile configuration

Systems and methods to zero a tile register pair

Systems and methods for performing instructions specifying ternary tile logic operations

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods for performing instructions to transform matrices into row-interleaved format

Systems and methods for performing instructions to transpose rectangular tiles

Systems, apparatuses, and methods for broadcast arithmetic operations

Systems and methods for implementing chained tile operations

Fixed point to floating point conversion

Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Systems, apparatuses, and methods for chained fused multiply add

Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits

Apparatus and method for low-latency invocation of accelerators

Fusion of processor micro-operations

Method and apparatus for merging binary translated basic blocks of instructions

Apparatuses, methods, and systems for 8-bit floating-point matrix dot product instructions

Matrix transpose and multiply

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods for performing nibble-sized operations on matrix elements

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

Systems, methods, and apparatuses for matrix operations

SPERBER ZEEV

Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits

Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits

Gather using index array and finite state machine

HUGHES CHRISTOPHER J

Gathering and scattering multiple data elements

RAIKIN SHLOMO

Gather cache architecture

VALENTINE ROBERT

Compressed instruction format

BEN-KIKI OREN

Apparatus and method for fast failure handling of instructions