P

Inventor

CORBAL JESUS

US160 patents
⚠️ This page may combine multiple inventors who share the name “CORBAL JESUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

46 patents
US11163565B2Nov 2, 2021

Systems, methods, and apparatuses for dot production operations

INTEL CORP24 citations98
US11086623B2Aug 10, 2021

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

INTEL CORP32 citations98
US10877756B2Dec 29, 2020

Systems, methods, and apparatuses for tile diagonal

INTEL CORP16 citations98
US10224954B1Mar 5, 2019

Floating point to fixed point conversion

INTEL CORP48 citations98
US12039332B2Jul 16, 2024

Systems, methods, and apparatus for matrix move

INTEL CORP7 citations94
US11977886B2May 7, 2024

Systems, methods, and apparatuses for tile store

INTEL CORP7 citations94
US11847452B2Dec 19, 2023

Systems, methods, and apparatus for tile configuration

INTEL CORP7 citations94
US11714642B2Aug 1, 2023

Systems, methods, and apparatuses for tile store

INTEL CORP7 citations94
US11567765B2Jan 31, 2023

Systems, methods, and apparatuses for tile load

INTEL CORP8 citations94
US11360770B2Jun 14, 2022

Systems, methods, and apparatuses for zeroing a matrix

INTEL CORP7 citations94
US11288069B2Mar 29, 2022

Systems, methods, and apparatuses for tile store

INTEL CORP7 citations94
US11288068B2Mar 29, 2022

Systems, methods, and apparatus for matrix move

INTEL CORP7 citations94
US11263008B2Mar 1, 2022

Systems, methods, and apparatuses for tile broadcast

INTEL CORP7 citations94
US11200055B2Dec 14, 2021

Systems, methods, and apparatuses for matrix add, subtract, and multiply

INTEL CORP14 citations94
US11093247B2Aug 17, 2021

Systems and methods to load a tile register pair

INTEL CORP22 citations94
US11080048B2Aug 3, 2021

Systems, methods, and apparatus for tile configuration

INTEL CORP14 citations94
US11023235B2Jun 1, 2021

Systems and methods to zero a tile register pair

INTEL CORP22 citations94
US10866786B2Dec 15, 2020

Systems and methods for performing instructions to transpose rectangular tiles

INTEL CORP27 citations94
US10846087B2Nov 24, 2020

Systems, apparatuses, and methods for broadcast arithmetic operations

INTEL CORP20 citations94
US10664287B2May 26, 2020

Systems and methods for implementing chained tile operations

INTEL CORP25 citations94
US10656942B2May 19, 2020

Fixed point to floating point conversion

INTEL CORP29 citations94
US7627735B2Dec 1, 2009

Implementing vector memory operations

INTEL CORP45 citations94
US10146535B2Dec 4, 2018

Systems, apparatuses, and methods for chained fused multiply add

INTEL CORP23 citations93
US10649772B2May 12, 2020

Method and apparatus for efficient matrix transpose

INTEL CORP29 citations89
US11816483B2Nov 14, 2023

Systems, methods, and apparatuses for matrix operations

INTEL CORP11 citations86
US11809869B2Nov 7, 2023

Systems and methods to store a tile register pair to memory

INTEL CORP12 citations86
US11789729B2Oct 17, 2023

Systems and methods for computing dot products of nibbles in two tile operands

INTEL CORP7 citations86
US11669326B2Jun 6, 2023

Systems, methods, and apparatuses for dot product operations

INTEL CORP15 citations86
US11609762B2Mar 21, 2023

Systems and methods to load a tile register pair

INTEL CORP7 citations86
US11416260B2Aug 16, 2022

Systems and methods for implementing chained tile operations

INTEL CORP9 citations86
US11403071B2Aug 2, 2022

Systems and methods for performing instructions to transpose rectangular tiles

INTEL CORP7 citations86
US11256504B2Feb 22, 2022

Apparatus and method for complex by complex conjugate multiplication

INTEL CORP11 citations86
US11693691B2Jul 4, 2023

Systems, methods, and apparatuses for heterogeneous computing

INTEL CORP4 citations85
US11645077B2May 9, 2023

Systems and methods to zero a tile register pair

INTEL CORP7 citations85
US11169802B2Nov 9, 2021

Systems, apparatuses, and methods for fused multiply add

INTEL CORP8 citations84
US11023231B2Jun 1, 2021

Systems and methods for executing a fused multiply-add instruction for complex numbers

INTEL CORP8 citations84
US10776699B2Sep 15, 2020

Optimized compute hardware for machine learning operations

INTEL CORP10 citations84
US10705839B2Jul 7, 2020

Apparatus and method for multiplying, summing, and accumulating sets of packed bytes

INTEL CORP9 citations84
US10223114B1Mar 5, 2019

Fixed point to floating point conversion

INTEL CORP8 citations84
US10133577B2Nov 20, 2018

Vector mask driven clock gating for power efficiency of a processor

INTEL CORP8 citations84
US11487541B2Nov 1, 2022

Systems, apparatuses, and methods for chained fused multiply add

INTEL CORP4 citations83
US11416281B2Aug 16, 2022

Systems, methods, and apparatuses for heterogeneous computing

INTEL CORP4 citations83
US11093277B2Aug 17, 2021

Systems, methods, and apparatuses for heterogeneous computing

INTEL CORP6 citations83
US10282296B2May 7, 2019

Zeroing a cache line

INTEL CORP7 citations83
US9411592B2Aug 9, 2016

Vector address conflict resolution with vector population count functionality

INTEL CORP11 citations83
US9411584B2Aug 9, 2016

Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality

INTEL CORP7 citations83

OULD-AHMED-VALL ELMOUSTAPHA

2 patents

HUGHES CHRISTOPHER J

1 patent

TOLL BRET L

1 patent

Showing the top 50 of 160 patents by PatentIndex Score.