Inventor
BONELLA RANDY M
US31 patents
⚠️ This page may combine multiple inventors who share the name “BONELLA RANDY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
19 patentsUS7024518B2Apr 4, 2006
Dual-port buffer-to-memory interface
INTEL CORP151 citations99
US6747887B2Jun 8, 2004
Memory module having buffer for isolating stacked memory devices
INTEL CORP128 citations99
US6742098B1May 25, 2004
Dual-port buffer-to-memory interface
INTEL CORP445 citations99
US6658509B1Dec 2, 2003
Multi-tier point-to-point ring memory interface
INTEL CORP373 citations99
US6553450B1Apr 22, 2003
Buffer to multiply memory interface
INTEL CORP310 citations99
US6493250B2Dec 10, 2002
Multi-tier point-to-point buffered memory interface
INTEL CORP223 citations99
US6487102B1Nov 26, 2002
Memory module having buffer for isolating stacked memory devices
INTEL CORP286 citations99
US6928571B1Aug 9, 2005
Digital system of adjusting delays on circuit boards
INTEL CORP116 citations98
US6820163B1Nov 16, 2004
Buffering data transfer between a chipset and memory modules
INTEL CORP118 citations98
US6625687B1Sep 23, 2003
Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
INTEL CORP324 citations98
US6530006B1Mar 4, 2003
System and method for providing reliable transmission in a buffered memory system
INTEL CORP112 citations98
US6449213B1Sep 10, 2002
Memory interface having source-synchronous command/address signaling
INTEL CORP115 citations98
US6317352B1Nov 13, 2001
Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
INTEL CORP522 citations98
US6697888B1Feb 24, 2004
Buffering and interleaving data transfer between a chipset and memory modules
INTEL CORP75 citations97
US6928593B1Aug 9, 2005
Memory module and memory component built-in self test
INTEL CORP46 citations92
US7249232B2Jul 24, 2007
Buffering and interleaving data transfer between a chipset and memory modules
INTEL CORP11 citations84
US6192459B1Feb 20, 2001
Method and apparatus for retrieving data from a data storage device
INTEL CORP10 citations74
US5818794AOct 6, 1998
Internally controlled signal system for controlling the operation of a device
INTEL CORP2 citations63
US6397291B2May 28, 2002
Method and apparatus for retrieving data from a data storage device
INTEL CORP0 citations52
COMPAQ COMPUTER CORP
10 patentsUS5537555AJul 16, 1996
Fully pipelined and highly concurrent memory controller
COMPAQ COMPUTER CORP128 citations98
US5471590ANov 28, 1995
Bus master arbitration circuitry having improved prioritization
COMPAQ COMPUTER CORP78 citations96
US5446863AAug 29, 1995
Cache snoop latency prevention apparatus
COMPAQ COMPUTER CORP53 citations96
US5325503AJun 28, 1994
Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line
COMPAQ COMPUTER CORP107 citations96
US5797020AAug 18, 1998
Bus master arbitration circuitry having improved prioritization
COMPAQ COMPUTER CORP31 citations92
US5333293AJul 26, 1994
Multiple input frequency memory controller
COMPAQ COMPUTER CORP31 citations92
US5625824AApr 29, 1997
Circuit for selectively preventing a microprocessor from posting write cycles
COMPAQ COMPUTER CORP17 citations81
US5404559AApr 4, 1995
Apparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycle
COMPAQ COMPUTER CORP10 citations74
US5790869AAug 4, 1998
Circuit for selectively preventing a microprocessor from posting write cycles
COMPAQ COMPUTER CORP11 citations72
US5253358AOct 12, 1993
Cache memory expansion and transparent interconnection
COMPAQ COMPUTER CORP15 citations70