Inventor

LEE JUNG-BAE

KR130 patents

⚠️ This page may combine multiple inventors who share the name “LEE JUNG-BAE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE JUNG-BAE

SAMSUNG ELECTRONICS CO LTD

System and method for selectively performing single-ended and differential signaling

Device and method for selecting power down exit

Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual rate mode operation and methods of operating same

Synchronous semiconductor memory device with double data rate scheme

Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same

Multimode data buffer and method for controlling propagation delay time

Integrated circuit memory devices having error checking and correction circuits therein and methods of operating same

Semiconductor memory device having write latency operation and method thereof

Methods and circuits for correcting a duty-cycle of a signal

Internal clock signal generator including circuit for accurately synchronizing internal clock signal with external clock signal

Synchronous DRAM having posted CAS latency and method for controlling CAS latency

Semiconductor memory device and driving signal generator therefor

Memory module and impedance calibration method of semiconductor memory device

On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having the same

Data input circuit and method for synchronous semiconductor memory device

High-speed data input circuit for a synchronous memory device

Stacked memory device

Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory

Memory module capable of improving the integrity of signals transmitted through a data bus and a command/address bus, and a memory system including the same

Semiconductor memory device and system outputting refresh flag

Semiconductor memory device having a fixed CAS latency and/or burst length

Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual data rate mode operation and methods of operating same

Input buffer circuits with input signal boost capability and methods of operation thereof

Phase locked delay circuit

Circuit for generating an internal clock for data output buffers in a synchronous DRAM devices

Data input circuit and method for synchronous semiconductor memory device

Internal voltage generation circuit having stable operating characteristics at low external supply voltages

Semiconductor memory device performing auto refresh in the self refresh mode

Semiconductor memory device capable of improving data processing speed and efficiency of a data input and output pin and related method for controlling read and write

Current-mode bidirectional input/output buffer

Memory devices with selective error correction code

Semiconductor memory device performing a refresh operation, and memory system including the same

Semiconductor memory device storing refresh period information and operating method thereof

Memory system and command handling method

Semiconductor memory module and semiconductor memory system having termination resistor units

Stacked semiconductor apparatus with configurable vertical I/O

Input buffer for detecting an input signal

Memory system having low power consumption

Memory system mounted directly on board and associated method

Video signal processing circuit having a bypass mode and display apparatus comprising the same

Memory systems, modules, controllers and methods using dedicated data and control busses

Memory system and data channel initialization method for memory system

Semiconductor memory devices and signal line arrangements and related methods

CHUNG HOE-JU

System and method for selectively performing single-ended and differential signaling

System and method for selectively performing single-ended and differential signaling

System and device with error detection/correction process and method outputting data

KIM HO-YOUNG

Semiconductor memory device having shared temperature control circuit

LEE JUNG BAE

Cosmetic case

PARK DUK-HA

Semiconductor memory device including refresh control circuit and method of refreshing the same

LEE DONG-HYUK

Row address code selection based on locations of substandard memory cells