Inventor
BARROW MICHAEL
US34 patents
⚠️ This page may combine multiple inventors who share the name “BARROW MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
24 patentsUS5898219AApr 27, 1999
Custom corner attach heat sink design for a plastic ball grid array integrated circuit package
INTEL CORP122 citations99
US5894410AApr 13, 1999
Perimeter matrix ball grid array circuit package with a populated center
INTEL CORP131 citations99
US5875102AFeb 23, 1999
Eclipse via in pad structure
INTEL CORP106 citations98
US6146921ANov 14, 2000
Cavity mold cap BGA package with post mold thermally conductive epoxy attach heat sink
INTEL CORP67 citations96
US5889655AMar 30, 1999
Integrated circuit package substrate with stepped solder mask openings
INTEL CORP62 citations96
US5796589AAug 18, 1998
Ball grid array integrated circuit package that has vias located within the solder pads of a package
INTEL CORP49 citations96
US5706178AJan 6, 1998
Ball grid array integrated circuit package that has vias located within the solder pads of a package
INTEL CORP90 citations96
US6747362B2Jun 8, 2004
Perimeter matrix ball grid array circuit package with a populated center
INTEL CORP19 citations92
US6521845B1Feb 18, 2003
Thermal spreading enhancements for motherboards using PBGAs
INTEL CORP40 citations92
US6297078B1Oct 2, 2001
Integrated circuit package with bond wires at the corners of an integrated circuit
INTEL CORP16 citations92
US5917702AJun 29, 1999
Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package
INTEL CORP23 citations92
US5880529AMar 9, 1999
Silicon metal-pillar conductors under stagger bond pads
INTEL CORP18 citations92
US5812379ASep 22, 1998
Small diameter ball grid array pad size for improved motherboard routing
INTEL CORP19 citations92
US5801450ASep 1, 1998
Variable pitch stagger die for optimal density
INTEL CORP30 citations92
US5936848AAug 10, 1999
Electronics package that has a substrate with an array of hollow vias and solder balls that are eccentrically located on the vias
INTEL CORP56 citations90
US6118182ASep 12, 2000
Integrated circuit package with rectangular contact pads
INTEL CORP17 citations84
US5867367AFeb 2, 1999
Quad flat pack integrated circuit package
INTEL CORP15 citations82
US6420651B1Jul 16, 2002
Integrated circuit package with bond wires at the corners of an integrated circuit
INTEL CORP7 citations74
US5978224ANov 2, 1999
Quad flat pack integrated circuit package
INTEL CORP9 citations74
US7543377B2Jun 9, 2009
Perimeter matrix ball grid array circuit package with a populated center
INTEL CORP1 citations63
US6498390B1Dec 24, 2002
Integrated circuit package that includes a thermally conductive tape which attaches a thermal element to a plastic housing
INTEL CORP5 citations63
US6255135B1Jul 3, 2001
Quad flat pack integrated circuit package
INTEL CORP3 citations63
US5949651ASep 7, 1999
Quad flat pack integrated circuit package
INTEL CORP3 citations63
US6110762AAug 29, 2000
Method of manufacturing a custom corner attach heat sink design for a plastic ball grid array integrated circuit package
INTEL CORP1 citations52
AMKOR TECHNOLOGY INC
5 patentsUS7898093B1Mar 1, 2011
Exposed die overmolded flip chip package and fabrication method
AMKOR TECHNOLOGY INC50 citations98
US8476748B1Jul 2, 2013
Exposed die overmolded flip chip package and fabrication method
AMKOR TECHNOLOGY INC15 citations92
US8847372B1Sep 30, 2014
Exposed die overmolded flip chip package and fabrication method
AMKOR TECHNOLOGY INC8 citations84
US8541260B1Sep 24, 2013
Exposed die overmolded flip chip package and fabrication method
AMKOR TECHNOLOGY INC7 citations84
US8368194B1Feb 5, 2013
Exposed die overmolded flip chip package
AMKOR TECHNOLOGY INC8 citations84