Inventor

PECHANEK GERALD G

US77 patents

⚠️ This page may combine multiple inventors who share the name “PECHANEK GERALD G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PECHANEK GERALD G

PTS CORP

Methods and apparatus for manifold array processing

Methods and apparatus for efficient complex long multiplication and covariance matrix implementation

Efficient complex multiplication and fast fourier transform (FFT) implementation on the manarray architecture

Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions

Methods and apparatus for power control in a scalable array of processor elements

Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit

Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor

Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

Methods and apparatus for scalable array processor interrupt detection and response

Methods and apparatus for ManArray PE-PE switch control

Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor

Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

Methods and apparatus for efficient cosine transform implementations

Specifying different type generalized event and action pair in a processor

IBM

Distributed processing array with component processors performing customized interpretation of instructions

Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier

Parallel processing system and method using surrogate instructions

Learning machine synapse processor system apparatus

Learning machine synapse processor system apparatus

Triangular scalable neural array processor

SPIN: a sequential pipeline neurocomputer

Pyramid learning architecture neurocomputer

Scalable neural array processor

Data processing system parallel data bus having a single oscillator clocking apparatus

Array processor communication architecture with broadcast processor instructions

Processor using folded array structures for transposition memory and fast cosine transform computation

Scalable neural array processor and method

Communicating adder tree system for neural array processor

BOPS INC

Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file

Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit

Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor

Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture

Methods and apparatus for instruction addressing in indirect VLIW processors

Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication

Methods and apparatus for manifold array processing

Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor

Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision

Methods and apparatus for dynamic instruction controlled reconfiguration register file with extended precision

BILLIONS OF OPERATIONS PER SEC

Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor

Method and apparatus for manifold array processing

Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication

Merged array controller and processing element

Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor

Methods and apparatus for manarray PE-PE switch control

Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

BILLION OF OPERATIONS PER SECO

Manifold array processor