Inventor
REVILLA JUAN GUILLERMO
US19 patents
⚠️ This page may combine multiple inventors who share the name “REVILLA JUAN GUILLERMO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
6 patentsUS6460120B1Oct 1, 2002
Network processor, memory organization and methods
IBM133 citations98
US6081860AJun 27, 2000
Address pipelining for data transfers
IBM92 citations98
US5925118AJul 20, 1999
Methods and architectures for overlapped read and write operations
IBM69 citations96
US5884051AMar 16, 1999
System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities
IBM61 citations95
US5862353AJan 19, 1999
Systems and methods for dynamically controlling a bus
IBM48 citations92
US5926831AJul 20, 1999
Methods and apparatus for control of speculative memory accesses
IBM18 citations84
BILLIONS OF OPERATIONS PER SEC
4 patentsUS6173389B1Jan 9, 2001
Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
BILLIONS OF OPERATIONS PER SEC207 citations99
US6151668ANov 21, 2000
Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication
BILLIONS OF OPERATIONS PER SEC108 citations98
US6216223B1Apr 10, 2001
Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
BILLIONS OF OPERATIONS PER SEC122 citations96
US6101592AAug 8, 2000
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
BILLIONS OF OPERATIONS PER SEC71 citations96
BOPS INC
4 patentsUS6557094B2Apr 29, 2003
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
BOPS INC48 citations96
US6321322B1Nov 20, 2001
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
BOPS INC35 citations96
US6446191B1Sep 3, 2002
Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication
BOPS INC48 citations95
US6467036B1Oct 15, 2002
Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
BOPS INC34 citations92
PTS CORP
3 patentsUS6851041B2Feb 1, 2005
Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
PTS CORP29 citations92
US6848041B2Jan 25, 2005
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
PTS CORP15 citations92
US6775766B2Aug 10, 2004
Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
PTS CORP29 citations92