Inventor
LARSEN LARRY D
US32 patents
⚠️ This page may combine multiple inventors who share the name “LARSEN LARRY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
10 patentsUS5659722AAug 19, 1997
Multiple condition code branching system in a multi-processor environment
IBM110 citations98
US6128720AOct 3, 2000
Distributed processing array with component processors performing customized interpretation of instructions
IBM167 citations97
US5682491AOct 28, 1997
Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
IBM179 citations97
US5649135AJul 15, 1997
Parallel processing system and method using surrogate instructions
IBM116 citations97
US5115500AMay 19, 1992
Plural incompatible instruction format decode method and apparatus
IBM81 citations96
US5659785AAug 19, 1997
Array processor communication architecture with broadcast processor instructions
IBM97 citations94
US5081574AJan 14, 1992
Branch control in a three phase pipelined signal processor
IBM47 citations92
US4794517ADec 27, 1988
Three phased pipelined signal processor
IBM69 citations92
US5371872ADec 6, 1994
Method and apparatus for controlling operation of a cache memory during an interrupt
IBM37 citations90
US4663675AMay 5, 1987
Apparatus and method for digital speech filing and retrieval
IBM9 citations73
ALTERA CORP
5 patentsUS7493474B1Feb 17, 2009
Methods and apparatus for transforming, loading, and executing super-set instructions
ALTERA CORP59 citations98
US7340591B1Mar 4, 2008
Providing parallel operand functions using register file and extra path storage
ALTERA CORP20 citations84
US7386710B2Jun 10, 2008
Methods and apparatus for scalable array processor interrupt detection and response
ALTERA CORP4 citations74
US7853779B2Dec 14, 2010
Methods and apparatus for scalable array processor interrupt detection and response
ALTERA CORP2 citations63
USRE40509ESep 16, 2008
Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture
ALTERA CORP4 citations63
BOPS INC
4 patentsUS6397324B1May 28, 2002
Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file
BOPS INC79 citations97
US6557094B2Apr 29, 2003
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
BOPS INC48 citations96
US6408382B1Jun 18, 2002
Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture
BOPS INC54 citations96
US6321322B1Nov 20, 2001
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
BOPS INC35 citations96
BARRY EDWIN FRANKLIN
4 patentsUS8489858B2Jul 16, 2013
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN5 citations84
US9158547B2Oct 13, 2015
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN1 citations63
US8751772B2Jun 10, 2014
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN0 citations52
US8161267B2Apr 17, 2012
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN0 citations52