Inventor

OKADA LYNNE A

US35 patents

Patents

35 patents

US6583046B1Jun 24, 2003

Post-treatment of low-k dielectric for prevention of photoresist poisoning

ADVANCED MICRO DEVICES INC67 citations96

US6534397B1Mar 18, 2003

Pre-treatment of low-k dielectric for prevention of photoresist poisoning

ADVANCED MICRO DEVICES INC56 citations96

US6475929B1Nov 5, 2002

Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant

ADVANCED MICRO DEVICES INC70 citations96

US6309955B1Oct 30, 2001

Method for using a CVD organic barc as a hard mask during via etch

ADVANCED MICRO DEVICES INC54 citations96

US6767827B1Jul 27, 2004

Method for forming dual inlaid structures for IC interconnections

ADVANCED MICRO DEVICES INC23 citations93

US6603206B2Aug 5, 2003

Slot via filled dual damascene interconnect structure without middle etch stop layer

ADVANCED MICRO DEVICES INC17 citations93

US6599839B1Jul 29, 2003

Plasma etch process for nonhomogenous film

ADVANCED MICRO DEVICES INC36 citations93

US6521524B1Feb 18, 2003

Via filled dual damascene structure with middle stop layer and method for making the same

ADVANCED MICRO DEVICES INC36 citations93

US6472231B1Oct 29, 2002

Dielectric layer with treated top surface forming an etch stop layer and method of making the same

ADVANCED MICRO DEVICES INC43 citations93

US6465889B1Oct 15, 2002

Silicon carbide barc in dual damascene processing

ADVANCED MICRO DEVICES INC32 citations93

US6372631B1Apr 16, 2002

Method of making a via filled dual damascene structure without middle stop layer

ADVANCED MICRO DEVICES INC29 citations93

US6872663B1Mar 29, 2005

Method for reworking a multi-layer photoresist following an underlayer development

ADVANCED MICRO DEVICES INC28 citations92

US6514860B1Feb 4, 2003

Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning

ADVANCED MICRO DEVICES INC15 citations84

US6492272B1Dec 10, 2002

Carrier gas modification for use in plasma ashing of photoresist

ADVANCED MICRO DEVICES INC15 citations84

US6451673B1Sep 17, 2002

Carrier gas modification for preservation of mask layer during plasma etching

ADVANCED MICRO DEVICES INC20 citations84

US6448654B1Sep 10, 2002

Ultra thin etch stop layer for damascene process

ADVANCED MICRO DEVICES INC16 citations84

US6383919B1May 7, 2002

Method of making a dual damascene structure without middle stop layer

ADVANCED MICRO DEVICES INC18 citations84

US7256499B1Aug 14, 2007

Ultra low dielectric constant integrated circuit system

ADVANCED MICRO DEVICES INC8 citations74

US6846749B1Jan 25, 2005

N-containing plasma etch process with reduced resist poisoning

ADVANCED MICRO DEVICES INC7 citations74

US6656830B1Dec 2, 2003

Dual damascene with silicon carbide middle etch stop layer/ARC

ADVANCED MICRO DEVICES INC12 citations74

US6495447B1Dec 17, 2002

Use of hydrogen doping for protection of low-k dielectric layers

ADVANCED MICRO DEVICES INC13 citations74

US6465340B1Oct 15, 2002

Via filled dual damascene structure with middle stop layer and method for making the same

ADVANCED MICRO DEVICES INC11 citations74

US6444573B1Sep 3, 2002

Method of making a slot via filled dual damascene structure with a middle stop layer

ADVANCED MICRO DEVICES INC8 citations74

US6429116B1Aug 6, 2002

Method of fabricating a slot dual damascene structure without middle stop layer

ADVANCED MICRO DEVICES INC12 citations74

US6372635B1Apr 16, 2002

Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer

ADVANCED MICRO DEVICES INC11 citations74

US6340395B1Jan 22, 2002

Salsa clean process

ADVANCED MICRO DEVICES INC8 citations65

US7279410B1Oct 9, 2007

Method for forming inlaid structures for IC interconnections

ADVANCED MICRO DEVICES INC3 citations63

US6756300B1Jun 29, 2004

Method for forming dual damascene interconnect structure

ADVANCED MICRO DEVICES INC6 citations63

US6610608B1Aug 26, 2003

Plasma etching using combination of CHF3 and CH3F

ADVANCED MICRO DEVICES INC4 citations63

US6391766B1May 21, 2002

Method of making a slot via filled dual damascene structure with middle stop layer

ADVANCED MICRO DEVICES INC3 citations63

US6365505B1Apr 2, 2002

Method of making a slot via filled dual damascene structure with middle stop layer

ADVANCED MICRO DEVICES INC6 citations63

OKADA LYNNE A

Patents

Post-treatment of low-k dielectric for prevention of photoresist poisoning

Pre-treatment of low-k dielectric for prevention of photoresist poisoning

Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant

Method for using a CVD organic barc as a hard mask during via etch

Method for forming dual inlaid structures for IC interconnections

Slot via filled dual damascene interconnect structure without middle etch stop layer

Plasma etch process for nonhomogenous film

Via filled dual damascene structure with middle stop layer and method for making the same

Dielectric layer with treated top surface forming an etch stop layer and method of making the same

Silicon carbide barc in dual damascene processing

Method of making a via filled dual damascene structure without middle stop layer

Method for reworking a multi-layer photoresist following an underlayer development

Integration of organic fill for dual damascene process

Vapor treatment for repairing damage of low-k dielectric

Sealing sidewall pores in low-k dielectrics

Dual damascene metal interconnect structure with dielectric studs

Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning

Carrier gas modification for use in plasma ashing of photoresist

Carrier gas modification for preservation of mask layer during plasma etching

Ultra thin etch stop layer for damascene process

Method of making a dual damascene structure without middle stop layer

Ultra low dielectric constant integrated circuit system

N-containing plasma etch process with reduced resist poisoning

Dual damascene with silicon carbide middle etch stop layer/ARC

Use of hydrogen doping for protection of low-k dielectric layers

Via filled dual damascene structure with middle stop layer and method for making the same

Method of making a slot via filled dual damascene structure with a middle stop layer

Method of fabricating a slot dual damascene structure without middle stop layer

Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer

Salsa clean process

Method for forming inlaid structures for IC interconnections

Method for forming dual damascene interconnect structure

Plasma etching using combination of CHF3 and CH3F

Method of making a slot via filled dual damascene structure with middle stop layer

Method of making a slot via filled dual damascene structure with middle stop layer