Inventor

CHONG YAN

US89 patents

⚠️ This page may combine multiple inventors who share the name “CHONG YAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHONG YAN

ALTERA CORP

Programmable I/O element circuit for high speed logic devices

Programmable logic integrated circuit devices with differential signaling capabilities

PVT compensated auto-calibration scheme for DDR3

PVT compensated auto-calibration scheme for DDR3

On/off reference voltage switch for multiple I/O standards

Input buffer for multiple differential I/O standards

Dual-port SRAM in a programmable logic device

Read-leveling implementations for DDR3 applications on an FPGA

Control circuit for self-compensating delay chain for multiple-data-rate interfaces

High-performance memory interface circuit architecture

Self-compensating delay chain for multiple-date-rate interfaces

Multiple data rate interface architecture

Loop circuitry with low-pass noise filter

Multiple data rate interface architecture

Schmitt trigger circuit with adjustable trip point voltages

Multiple data rate interface architecture

I/O block for high performance memory interfaces

Method and apparatus for minimizing skew between signals

Digitally controlled delay-locked loops

Method and apparatus for quantifying and minimizing skew between signals

Input buffer for multiple differential I/O standards

Input buffer for multiple differential I/O standards

Dual-port SRAM in a programmable logic device

Parallel programming of programmable logic using register chains

Supply voltage detection circuit

Circuit for providing clock signals with low skew

Circuit design technique for DQS enable/disable calibration

Input-output circuitry for integrated circuits

Techniques for providing multiple delay paths in a delay circuit

Write-side calibration for data interface

Read-side calibration for data interface

Innovated technique to reduce memory interface write mode SSN in FPGA

Innovated technique to reduce memory interface write mode SSN in FPGA

Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices

Loop circuitry with low-pass noise filter

Methods and apparatus for clock tree phase alignment

Clock structure with calibration circuitry

Multiple data rate interface architecture

DLL with adjustable phase shift using processed control signal

CHONG YAN

Circuit design technique for DQS enable/disable calibration

Duty cycle correction circuit for memory interfaces in integrated circuits

Write-leveling implementation in programmable logic devices

AMPERE COMPUTING LLC

Variation immune on-die voltage droop detector

Self-referenced on-die voltage droop detector

NAGARAJAN PRADEEP

Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop

Techniques for providing reduced duty cycle distortion

WANG BONNIE I

On-die input reference voltage with self-calibrating duty cycle correction

LU SEAN SHAU-TU

Variation compensation circuitry for memory interface

HUANG JOSEPH

High performance memory interface circuit architecture

PAN PHILIP

Multiple data rate interface architecture