Inventor

CHOY JON S

US45 patents

⚠️ This page may combine multiple inventors who share the name “CHOY JON S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOY JON S

FREESCALE SEMICONDUCTOR INC

Nonvolatile static random access memory (NVSRAM) system having a static random access memory (SRAM) array and a resistive memory array

Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor

Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor

Slew rate control of a charge pump

Charge pump system with reduced ripple and method therefor

Systems and methods for driving a control gate with a select gate signal in a split-gate nonvolatile memory cell

High-dynamic range low ripple voltage multiplier

Multi-level voltage adjustment

Concurrent programming and program verification of floating gate transistor

Nonvolatile memory having latching sense amplifier and method of operation

Voltage sampling switch and method therefor

Negative charge pump regulation

Integrated circuit having a non-volatile memory with discharge rate control and method therefor

Charge pump circuit for providing multiplied voltage

Integrated circuit having a non-volatile memory with discharge rate control and method therefor

Non-volatile memory having a bias on the source electrode for HCI programming

Non-volatile memory architecture and method thereof

Method of accessing memory and device thereof

Sense amplifier

Method and circuit for preventing high voltage memory disturb

Memory circuit using a reference for sensing

Soft program of a non-volatile memory block

Erase ramp pulse width control for non-volatile memory

Current comparison based voltage bias generator for electronic data storage devices

Voltage regulator for integrated circuits

Regulator having interleaved latches

Non-volatile memory having a multiple block erase mode and method therefor

Simulation of hierarchical circuit element arrays

CHOY JON S

Flash memory with bias voltage for word line/row driver

Latching level shifter and method of operation

Systems and methods for controlling power in semiconductor circuits

Voltage ramp-up protection

Current injector circuit for supplying a load transient in an integrated circuit

Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor

Sense amplifier voltage regulator

Error detection at an oscillator

Control gate driver for use with split gate memory cells

Method for programming a multi-state non-volatile memory (NVM)

EGUCHI RICHARD K

Temperature-based adaptive erase or program parallelism

Non-volatile memory robust start-up using analog-to-digital converter

Non-volatile memory (NVM) erase operation with brownout recovery technique

NXP USA INC

Charge pump circuit for providing multiplied voltage

Sense amplifier

ROY ANIRBAN

Flash memory with improved read performance

NETO FERNANDO Z

Latched comparator and methods therefor