Inventor

KIM UNSOON

US53 patents

⚠️ This page may combine multiple inventors who share the name “KIM UNSOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM UNSOON

ADVANCED MICRO DEVICES INC

Core array and periphery isolation technique

Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device

Process for fabricating an integrated circuit with a self-aligned contact

Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space

Isolation boundaries in flash memory cores

Flash memory cell with minimized floating gate to drain/source overlap for minimizing charge leakage

Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device

System and method for improving reliability in a semiconductor device

Self-aligned gate formation using polysilicon polish with peripheral protective layer

Hard mask removal process including isolation dielectric refill

Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core

Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird&#39;s beak formation for high performance flash memory devices

Flash memory gate coupling using HSG polysilicon

Non-volatile memory dielectric as charge pump dielectric

Method and system for providing a contact on a semiconductor device

Self-aligned polysilicon polish

Shallow trench isolation spacer for weff improvement

Memory device having improved periphery and core isolation

Process for fabricating an integrated circuit with a self-aligned contact

Shallow trench isolation fill process

CYPRESS SEMICONDUCTOR CORP

Split-gate flash cell formed on recessed substrate

Memory first process flow and device

Method of forming high-voltage transistor with thin gate poly

Embedded non-volatile memory device and fabrication method of the same

Method of forming high-voltage transistor with thin gate poly

Memory first process flow and device

Charge trapping split gate device and method of fabricating same

Method of forming high-voltage transistor with thin gate poly

Memory first process flow and device

Memory first process flow and device

Split-gate flash cell formed on recessed substrate

Memory first process flow and device

Manufacturing of FET devices having lightly doped drain and source regions

Three dimensional capacitor

Charge trapping split gate device and method of fabricating same

SPANSION LLC

Memory first process flow and device

System and method for improving mesa width in a semiconductor device

Memory gate landing pad made from dummy features

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device

Shallow trench isolation approach for improved STI corner rounding

Non-critical complementary masking method for poly-1 definition in flash memory device fabrication

Flash memory cells having trenched storage elements

Dual storage node memory devices and methods for fabricating the same

Method for controlling poly 1 thickness and uniformity in a memory array fabrication process

WU YIDER

System and method for improving reliability in a semiconductor device

System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device

ZHENG WEI

Flash memory cells having trenched storage elements

LEE CHUNGHO

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

KIM UNSOON

System and method for improving mesa width in a semiconductor device

Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices