Inventor

MARATHE AMIT P

US46 patents

⚠️ This page may combine multiple inventors who share the name “MARATHE AMIT P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MARATHE AMIT P

ADVANCED MICRO DEVICES INC

Interconnect test structure with slotted feeder lines to prevent stress-induced voids

Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures

Method of semiconductor via testing

Methods of forming capped copper interconnects with improved electromigration resistance

Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP

Via formation in integrated circuit interconnects

Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance

Structure and method of semiconductor via testing

Method of improving electromigration resistance of capped Cu

Integrated circuit design system

Cu interconnects with composite barrier layers for wafer-to-wafer uniformity

System and method for current-enhanced stress-migration testing of interconnect

Determination of permeability of layer material within interconnect

Structure, system, and method for assessing electromigration permeability of layer material within interconnect

Copper interconnect with improved barrier layer

Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant

Semiconductor device having a multi-layer metal interconnect structure

Quantifying and predicting the impact of line edge roughness on device reliability and performance

Use of Ta-capped metal line to improve formation of memory element films

Hot carrier oxide qualification method

Selective deposition in integrated circuit interconnects

Void eliminating seed layer and conductor core integrated circuit interconnects

Predicting EM reliability by decoupling extrinsic and intrinsic sigma

Test structure for determining electromigration and interlayer dielectric failure

Method for forming conductor reservoir volume for integrated circuit interconnects

Use of an alloying element to form a stable oxide layer on the surface of metal features

Method of manufacturing a seed layer with annealed region for integrated circuit interconnects

Characterization of barrier layers in integrated circuit interconnects

Seed layer with annealed region for integrated circuit interconnects

Conductor reservoir volume for integrated circuit interconnects

Coherent alloy diffusion barrier for integrated circuit interconnects

Method for determining metal concentration in a field area

Sensitive technique for metal-void detection

Coherent carbide diffusion barrier for integrated circuit interconnects

Method and system for Joule heating characterization

Maximum VCC calculation method for hot carrier qualification

Coherent diffusion barriers for integrated circuit interconnects

Electro-chemical metal alloying for semiconductor manufacturing

Testing dielectric and barrier layers for integrated circuit interconnects

Elimination of flux divergence in integrated circuit interconnects

Gradated barrier layer in integrated circuit interconnects

Integrated circuit interconnect shunt layer

Method for forming an alloyed metal conductive element of an integrated circuit

SPANSION LLC

Use of Ta-capped metal line to improve formation of memory element films

GLOBALFOUNDRIES INC

Dielectric breakdown lifetime enhancement using alternating current (AC) capacitance

YIANG KOK YONG

Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer