Inventor

CLEVENGER LAWRENCE A

US628 patents

⚠️ This page may combine multiple inventors who share the name “CLEVENGER LAWRENCE A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CLEVENGER LAWRENCE A

IBM

Method for maximizing air gap in back end of the line interconnect through via landing modification

Stacked transistors with different channel widths

Self-trimming method on looped patterns

Chip packaging system and method using deposited diamond film

Structure and method for monitoring stress-induced degradation of conductive interconnects

Method and structure for providing improved thermal conduction for silicon semiconductor devices

Semiconductor chip using both polysilicon and metal gate devices

Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

Three-dimensional island pixel photo-sensor

Semi-sacrificial diamond for air dielectric formation

Semi-sacrificial diamond for air dielectric formation

Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen

Method and structure for providing improved thermal conduction for silicon semiconductor devices

Multi-chip package structures with discrete redistribution layers

Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers

Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

Caller identity verification based on unique multi-device signatures

Multiple width nanosheet devices

Fully aligned via employing selective metal deposition

Skip via for metal interconnects

Structures and methods for embedded magnetic random access memory (MRAM) fabrication

Fully aligned via with integrated air gaps

Self aligned pattern formation post spacer etchback in tight pitch configurations

Skip-vias bypassing a metallization level at minimum pitch

Stacked planar capacitors with scaled EOT

Middle of line cobalt interconnection

Interlayer via

Thin film for a multilayer semiconductor device for improving thermal stability and a method thereof

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Surface nitridation in metal interconnects

Metal fill optimization for self-aligned double patterning

Airgap protection layer for via alignment

High density planar magnetic domain wall memory apparatus

Structure for stochastic integrated circuit personalization

Method of forming high density planar magnetic domain wall memory

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

MIM capacitor and method of fabricating same

Electrical programmable metal resistor

Three-dimensional island pixel photo-sensor

Method to fabricate passive components using conductive polymer

Metal spacer gate for CMOS FET

Integrated metal-insulator-metal capacitor and metal gate transistor

High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits

High dielectric constant materials as gate dielectrics (insulators)

High dielectric constant materials forming components of DRAM storage cells

Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor

RFID tag with environmental sensor

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

CLEVENGER LAWRENCE A

Method for air gap interconnect integration using photo-patternable low k material

GLOBALFOUNDRIES INC

Method of forming self-aligned metal lines and vias