Inventor
LANZILLO NICHOLAS A
US19 patents
Patents
19 patentsUS10319629B1Jun 11, 2019
Skip via for metal interconnects
IBM25 citations94
US10243020B1Mar 26, 2019
Structures and methods for embedded magnetic random access memory (MRAM) fabrication
IBM18 citations94
US9985199B1May 29, 2018
Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield
IBM8 citations84
US10770511B2Sep 8, 2020
Structures and methods for embedded magnetic random access memory (MRAM) fabrication
IBM3 citations73
US10746782B2Aug 18, 2020
Accelerated wafer testing using non-destructive and localized stress
IBM4 citations73
US10739397B2Aug 11, 2020
Accelerated wafer testing using non-destructive and localized stress
IBM2 citations73
US10553789B1Feb 4, 2020
Fully aligned semiconductor device with a skip-level via
IBM4 citations73
US10256191B2Apr 9, 2019
Hybrid dielectric scheme for varying liner thickness and manganese concentration
IBM4 citations73
US9941211B1Apr 10, 2018
Reducing metallic interconnect resistivity through application of mechanical strain
IBM3 citations73
US11223655B2Jan 11, 2022
Semiconductor tool matching and manufacturing management in a blockchain
IBM4 citations72
US10796833B2Oct 6, 2020
Magnetic tunnel junction with low series resistance
IBM2 citations72
US11869783B2Jan 9, 2024
Optimizating semiconductor binning by feed-forward process adjustment
IBM0 citations62
US11348872B2May 31, 2022
Hybrid dielectric scheme for varying liner thickness and manganese concentration
IBM0 citations62
US11049744B2Jun 29, 2021
Optimizing semiconductor binning by feed-forward process adjustment
IBM0 citations62
US10978393B2Apr 13, 2021
Hybrid dielectric scheme for varying liner thickness and manganese concentration
IBM0 citations62
US10978342B2Apr 13, 2021
Interconnect with self-forming wrap-all-around barrier layer
IBM0 citations62
US10741751B2Aug 11, 2020
Fully aligned semiconductor device with a skip-level via
IBM1 citations62
US10720567B2Jul 21, 2020
Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield
IBM1 citations62
US10211155B2Feb 19, 2019
Reducing metallic interconnect resistivity through application of mechanical strain
IBM0 citations52