Inventor

RIZZOLO MICHAEL

US208 patents

⚠️ This page may combine multiple inventors who share the name “RIZZOLO MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RIZZOLO MICHAEL

IBM

Method for maximizing air gap in back end of the line interconnect through via landing modification

Formation of embedded magnetic random-access memory devices

Fully aligned via employing selective metal deposition

Structures and methods for embedded magnetic random access memory (MRAM) fabrication

Fully aligned via with integrated air gaps

Skip-vias bypassing a metallization level at minimum pitch

Airgap protection layer for via alignment

Pillar-based memory hardmask smoothing and stress reduction

Encapsulation topography-assisted self-aligned MRAM top contact

Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material

Selective dielectric deposition to prevent gouging in MRAM

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Method of manufacturing self-aligned interconnects by deposition of a non-conformal air-gap forming layer having an undulated upper surface

Wraparound top electrode line for crossbar array resistive switching device

Enabling low resistance gates and contacts integrated with bilayer dielectrics

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Bottom electrode for MRAM applications

Skip-vias bypassing a metallization level at minimum pitch

Social media modification of behavior and mobile screening for impairment

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield

Fold over emitter and collector field emission transistor

Integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects

Health monitoring using parallel cognitive processing

Forming deep airgaps without flop over

Heterogeneous metallization using solid diffusion removal of metal interconnects

Smartwatch blackbox

Hybrid metal interconnects with a bamboo grain microstructure

Uniform dielectric recess depth during fin reveal

Self aligned via and pillar cut for at least a self aligned double pitch

Fold over emitter and collector field emission transistor

Security key system

Structure and fabrication method for electromigration immortal nanoscale interconnects

Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects

Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zones

Embedded memory devices

Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features

Increasing cost benefit and energy efficiency with modular delivery drones in inclement weather

Alignment through topography on intermediate component for memory device patterning

Preserving underlying dielectric layer during MRAM device formation

Laser anneal for MRAM encapsulation enhancement

Selective CVD alignment-mark topography assist for non-volatile memory

Dynamic rigidity mechanism

Resistive memory crossbar array with ruthenium protection layer

TESSERA INC

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Selective ILD deposition for fully aligned via with airgap

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Selective ILD deposition for fully aligned via with airgap

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

TESSERA LLC

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device