Inventor

PADMANABHAN GOBI R

US32 patents

⚠️ This page may combine multiple inventors who share the name “PADMANABHAN GOBI R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PADMANABHAN GOBI R

NAT SEMICONDUCTOR CORP

Method of forming a vertical MOS transistor

Semiconductor die with heat and electrical pipes

Semiconductor sensor device using MEMS technology

High Q inductor in multi-level interconnect

Integrated circuit and method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip

Silicon die with metal feed through structure

Method and system for dynamically adjusting field of view in a capsule endoscope

MEMS semiconductor sensor device

Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process

Method of dicing a semiconductor wafer that substantially reduces the width of the saw street

Sensor configuration for a capsule endoscope

Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect

Method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip

Vertical MOS transistor

Radiation hardened MOS transistor

Method of forming a semiconductor die with heat and electrical pipes

Method of forming a metal interconnect with capacitive structures that adjust the capacitance of the interconnect

Method of forming a MOS transistor with a litho-less gate

Single-crystal silicon semiconductor structure

Hermetic seal for silicon die with metal feed through structure

Deep submicron MOS transistor with increased threshold voltage

Method of forming a hermetic seal for silicon die with metal feed through structure

LSI LOGIC CORP

Array of solder pads on an integrated circuit

Programmable polysilicon gate array base cell architecture

Semiconductor chip package with interconnect layers and routing and testing methods

Method of forming a high electromigration resistant metallization system

Semiconductor chip having identification/encryption code

Method of making a barrier metal technology for tungsten plug interconnection

Barrier metal technology for tungsten plug interconnection

Method of making buried metallization structure

Method of fabricating a programmable polysilicon gate array base cell structure

PADMANABHAN GOBI R

Semiconductor wafer and die that include an integrated circuit and two or more different MEMS-based semiconductor devices