Inventor
KODALAPURA NAGARAJU N
US5 patents
Patents
5 patentsUS10116436B1Oct 30, 2018
Techniques for preventing memory timing attacks
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US11144468B2Oct 12, 2021
Hardware based technique to prevent critical fine-grained cache side-channel attacks
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US11121853B2Sep 14, 2021
Techniques for preventing memory timing attacks
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US11777705B2Oct 3, 2023
Techniques for preventing memory timing attacks
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US10318440B2Jun 11, 2019
Mapping security policy group registers
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