Inventor

LIN KENG-CHU

TW172 patents

⚠️ This page may combine multiple inventors who share the name “LIN KENG-CHU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN KENG-CHU

TAIWAN SEMICONDUCTOR MFG CO LTD

Inner spacers for gate-all-around semiconductor devices

Structure and formation method of semiconductor device with high contact area

Epitaxial backside contact

Method and structure for barrier-less plug

Dummy fin structures and methods of forming same

Semiconductor device

Back-end-of-line (BEOL) interconnect structure

Semiconductor devices including conductive features with capping layers and methods of forming the same

Inner spacers for gate-all-around semiconductor devices

Semiconductor device structure with high contact area

Dummy fin structures and methods of forming same

Semiconductor device and manufacturing method thereof

Fin field effect transistor device structure and method for forming the same

Low resistance fill metal layer material as stressor in metal gates

Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure

Dummy fin structures and methods of forming same

Interconnect structures and methods of forming the same

Semiconductor device and manufacturing method thereof

Dielectric plugs

Photoresist and method of formation and use

Device and method of dielectric layer

Support structure for barrier layer of semiconductor device

Seal material for air gaps in semiconductor devices

Dual channel structure

Seal material for air gaps in semiconductor devices

Flowable films and methods of forming flowable films

Low thermal budget dielectric for semiconductor devices

Gate structures for stacked semiconductor devices

TAIWAN SEMICONDUCTOR MFG

Sealing pores of low-k dielectrics using CxHy

Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers

Integration scheme for Cu/low-k interconnects

Multi-step plasma treatment method to improve CU interconnect electrical performance

Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties

Method for avoiding photoresist resist residue on semioconductor feature sidewalls

Photoresist and method of formation and use

Back-end-of-line (BEOL) interconnect structure

Hard mask for back-end-of-line (BEOL) interconnect structure

Method for forming self-assembled mono-layer liner for Cu/porous low-k interconnections

Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio

Method of forming a shallow trench isolation structure

CxHy sacrificial layer for cu/low-k interconnects

Multi-level semiconductor device with capping layer for improved adhesion

Extreme low-k dielectric film scheme for advanced interconnect

VANGUARD INT SEMICONDUCT CORP

Method for fabricating an oxynitride layer having anti-reflective properties and low leakage current

High stress oxide to eliminate BPSG/SiN cracking

SHIH PO-CHENG

Double patterning strategy for contact hole and trench in photolithography

Methods for forming interconnect structures of integrated circuits

KO CHUNG-CHI

Double patterning strategy for contact hole and trench in photolithography

LIOU JOUNG-WEI

Low-K dielectric layer and porogen

Yang hui-chun

Semiconductor devices including conductive features with capping layers and methods of forming the same