Inventor

HELVEY TIMOTHY D

US18 patents

⚠️ This page may combine multiple inventors who share the name “HELVEY TIMOTHY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HELVEY TIMOTHY D

IBM

Replicating timing data in static timing analysis operation

Analyzing sparse wiring areas of an integrated circuit design

Changing the location of a buffer bay in a netlist

Analyzing timing requirements of a hierarchical integrated circuit design

Implementing enhanced physical design quality using historical placement analytics

Implementing enhanced physical design quality using historical placement analytics

Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros

Implementing Z directional macro port assignment

Determining positions of storage elements in a logic design

Concurrently modeling delays between points in static timing analysis operation

DAEDE RONALD J

Slack-based timing budget apportionment

Slack-based timing budget apportionment

DARSOW CRAIG M

Implementing timing pessimism reduction for parallel clock trees

Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip

ELLAVSKY MATTHEW R

Changing the location of a buffer bay in a netlist

Implementing Z directional macro port assignment

CURTIS PAUL G

Implementing net routing with enhanced correlation of pre-buffered and post-buffered routes

BENJAMIN SAMUEL R

Swapping ports to change the timing window overlap of adjacent nets