Inventor

GREBS THOMAS E

US35 patents

⚠️ This page may combine multiple inventors who share the name “GREBS THOMAS E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GREBS THOMAS E

FAIRCHILD SEMICONDUCTOR

Trench-gate field effect transistors and methods of forming the same

Trench-gated FET for power device with active gate trenches and gate runner trench utilizing one-mask etch

Semiconductor power device having a top-side drain using a sinker trench

Simplified ozonator for a semiconductor wafer cleaner

Process for forming MOS-gated power device having segmented trench and extended doping zone

MOS-gated power device having segmented trench and extended doping zone and process for forming same

Methods for forming shielded gate field effect transistors

Buried gate-field termination structure

Method of forming trench-gate field effect transistors

Semiconductor power device having a top-side drain using a sinker trench

Trench-gate field effect transistor with channel enhancement region and methods of forming the same

Trench FET with improved body to gate alignment

MOS-gated power device with doped polysilicon body and process for forming same

Trench etch with incremental oxygen flow

Trench-gate field effect transistor

MOS-gated power device with doped polysilicon body and process for forming same

Method for forming shielded gate field effect transistor using spacers

Power transistor with trench sinker for contacting the backside

Reduced process sensitivity of electrode-semiconductor rectifiers

Potted transducer array with matching network in a multiple pass configuration

Potted transducer array with matching network in a multiple pass configuration

Lateral MOSFET with substrate drain connection

GREBS THOMAS E

Shielded gate field effect transistors

Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices

Trench-shielded semiconductor device

Method of forming shielded gate power transistor utilizing chemical mechanical planarization

Charge balance semiconductor devices with increased mobility structures

Trench MOS barrier schottky rectifier with a planar surface using CMP techniques

Trench MOS barrier schottky rectifier with a planar surface using CMP techniques

Semiconductor power device having a top-side drain using a sinker trench

Multi-level options for power MOSFETS

YILMAZ HAMZA

Structure and method for forming trench-gate field effect transistor with source plug

HARRIS CORP

Method of fabricating UMOS semiconductor devices using a self-aligned, reduced mask process

YEDINAK JOSEPH A

Reduced process sensitivity of electrode-semiconductor rectifiers

YEDINAK JOSEPH

Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same