Inventor

OUELLETTE MICHAEL R

US102 patents

⚠️ This page may combine multiple inventors who share the name “OUELLETTE MICHAEL R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OUELLETTE MICHAEL R

IBM

Method of electrically blowing fuses under control of an on-chip tester interface apparatus

Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure

Automatic shutdown or throttling of a bist state machine using thermal feedback

Electronic fuse blow mimic and methods for adjusting electronic fuse blow

Low voltage programmable eFuse with differential sensing scheme

Compilable address magnitude comparator for memory array self-testing

Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories

Multiple on-chip test runs and repairs for memories

Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability

Compilable address magnitude comparator for memory array self-testing

Bi-directional differential low power sense amp and memory system

Performance optimizing compiler for building a compiled SRAM

Memory testing

Self-test architecture to implement data column redundancy in a RAM

Automation of fuse compression for an ASIC design system

Automated fuse blow software system

Precharged wordline decoder with locally-controlled clock

Diagnosable general purpose test registers scan chain design

Structure for system for and method of performing high speed memory diagnostics via built-in-self-test

System and method for performing high speed memory diagnostics via built-in-self-test

System and method for differential eFUSE sensing without reference fuses

Method for reduced electrical fusing time

Memory BIST and repair

Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

Method and apparatus of local word-line redundancy in CAM

Embedded CAM test structure for fully testing all matchlines

Self-test method for testing read stability in a dual-port SRAM cell

Random access memory having an adaptable latency

System and method of reducing test time via address aware BIST circuitry

Partial good integrated circuit and method of testing same

Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories

Variable column redundancy region boundaries in SRAM

Method and apparatus for in-system redundant array repair on integrated circuits

Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

Saving content addressable memory power through conditional comparisons

Staggered start of BIST controllers and BIST engines

Integration of LBIST into array BISR flow

Read only memory (ROM) with redundancy

Decreasing power supply demand during BIST initializations

GORMAN KEVIN W

Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture

Structure and method for storing multiple repair pass data into a fusebay

OUELLETTE MICHAEL R

Determining fusebay storage element usage

Circuit and method for asynchronous pipeline processing with variable request signal delay

INTERNAITONAL BUSINESS MACHINE

Serial input shift register built-in self test circuit for embedded circuits

ANAND DARREN L

Fusebay controller structure, system, and method

GLOBALFOUNDRIES INC

Failure analysis and repair register sharing for memory BIST

BRACERAS GEORGE M

Read only memory (ROM) with redundancy

BARWIN JOHN E

Integrated circuit design method and system

LUKE SHAWN M

Security-enhanced radio frequency object locator system, method and program storage device