Inventor

NEMOUCHI FABRICE

FR36 patents

⚠️ This page may combine multiple inventors who share the name “NEMOUCHI FABRICE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NEMOUCHI FABRICE

COMMISSARIAT ENERGIE ATOMIQUE

Selective formation of a compound comprising a semi-conducting material and a metallic material in a substrate through a germanium oxide layer

Contact on a heterogeneous semiconductor substrate

Method of manufacturing microelectronic components

Method for fabricating an integrated circuit including a NMOS transistor and a PMOS transistor

Forming of a MOS transistor based on a two-dimensional semiconductor material

Method of making a quantum device

Method for forming metallic materials comprising semi-conductors

Device comprising spacers including a localised airgap and associated manufacturing methods

Method for producing a component by filling a cavity within an electrical isolation area with carbon-based material

Internal via with improved contact for upper semi-conductor layer of a 3D circuit

Semiconductor device and associated manufacturing method

Method for producing at least one device in compressive strained semiconductor

Method for manufacturing an electronic component having multiple quantum dots

Fabrication method of a transistor with improved field effect

Quantum device and method for producing the same

SBFET transistor and corresponding fabrication process

Transistor with MIS connections and fabricating process

Method for making an electronic device with superconductor qubit(s) including at least one JoFET

Method for producing a superconducting vanadium silicide on a silicon layer

Method for fabricating a heterostructure comprising active or passive elementary structure made of III-V material on the surface of a silicon-based substrate

Process for producing a component comprising III-V materials and contacts compatible with silicon process flows

Fabrication method of a stack of electronic devices

Semiconductor and metal alloy interconnections for a 3D circuit

Josephson transistor

Transistor having blocks of source and drain silicides near the channel

Formation of Ohmic contacts for a device provided with a region made of III-V material and a region made of another semiconductor material

Method for manufacturing a microelectronic device including depositing identical or different metallic layers on the same wafer

Process for producing an intermetallic contact based on Ni on InxGa1-xAs

NEMOUCHI FABRICE

Method of producing a device with transistors strained by means of an external layer

Method for preparing a layer comprising nickel monosilicide NiSi on a substrate comprising silicon

Manufacturing method for a device with transistors strained by silicidation of source and drain zones

GAILLARD FREDERIC-XAVIER

Method for producing a substrate including a step of thinning with stop when a porous zone is detected

Method for producing an electro-mechanical microsystem

DESPLOBAIN SEBASTIEN

Method for forming a multilayer structure

ST MICROELECTRONICS SA

Method for forming gate, source, and drain contacts on a MOS transistor

COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Method for making a quantum device