Inventor
SINHA SUBARNAREKHA
US22 patents
⚠️ This page may combine multiple inventors who share the name “SINHA SUBARNAREKHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
13 patentsUS7509622B2Mar 24, 2009
Dummy filling technique for improved planarization of chip surface topography
SYNOPSYS INC243 citations98
US7346865B2Mar 18, 2008
Fast evaluation of average critical area for IC layouts
SYNOPSYS INC23 citations92
US7503029B2Mar 10, 2009
Identifying layout regions susceptible to fabrication issues by using range patterns
SYNOPSYS INC27 citations91
US8601419B1Dec 3, 2013
Accurate process hotspot detection using critical design rule extraction
SYNOPSYS INC27 citations88
US8006212B2Aug 23, 2011
Method and system for facilitating floorplanning for 3D IC
SYNOPSYS INC14 citations84
US7703067B2Apr 20, 2010
Range pattern definition of susceptibility of layout regions to fabrication issues
SYNOPSYS INC10 citations84
US7543255B2Jun 2, 2009
Method and apparatus to reduce random yield loss
SYNOPSYS INC8 citations84
US7679872B2Mar 16, 2010
Electrostatic-discharge protection using a micro-electromechanical-system switch
SYNOPSYS INC7 citations73
US9098649B2Aug 4, 2015
Distance metric for accurate lithographic hotspot classification using radial and angular functions
SYNOPSYS INC5 citations72
US8000826B2Aug 16, 2011
Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
SYNOPSYS INC4 citations62
US7962873B2Jun 14, 2011
Fast evaluation of average critical area for ic layouts
SYNOPSYS INC2 citations62
US7962882B2Jun 14, 2011
Fast evaluation of average critical area for IC layouts
SYNOPSYS INC1 citations62
US7496883B2Feb 24, 2009
Method and apparatus for identifying and correcting phase conflicts
SYNOPSYS INC0 citations52
SINHA SUBARNAREKHA
3 patentsUS8219941B2Jul 10, 2012
Range pattern definition of susceptibility of layout regions to fabrication issues
SINHA SUBARNAREKHA6 citations82
US8209639B2Jun 26, 2012
Identifying layout regions susceptible to fabrication issues by using range patterns
SINHA SUBARNAREKHA3 citations60
US8141007B2Mar 20, 2012
Method and apparatus for identifying and correcting phase conflicts
SINHA SUBARNAREKHA1 citations50