Inventor

KOU YU

US60 patents

⚠️ This page may combine multiple inventors who share the name “KOU YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOU YU

SK HYNIX MEMORY SOLUTIONS INC

Probability maximum transition run codes

Margining decoding utilizing soft-inputs

Defect scan and manufacture test

Multiple interleavers in a coding system

LDPC selective decoding scheduling using a cost function

Manufacturing testing for LDPC codes

Manufacturing testing for LDPC codes

Buffer management in a turbo equalization system

LDPC decoding with on the fly error recovery

Error recovery using erasures for NAND Flash

Peel decoding for concatenated codes

Matching signal dynamic range for turbo equalization system

KOU YU

Interleaving parity bits into user bits to guarantee run-length constraint

Error recovery using erasures for NAND flash

Defect scan and manufacture test

Manufacturing testing for LDPC codes

Programmable LBA and dummy bit reliabilities

Manufacturing testing for LDPC codes

Manufacturing testing for LDPC codes

ETOPUS TECH INC

Timing recovery for digital receiver with interleaved analog-to-digital converters

Timing recovery for digital receiver with interleaved analog-to-digital converters

Sampling clock adjustment for an analog to digital converter of a receiver

Receiver for high speed communication channel

Receiver for high speed communication channel

Receiver for high speed communication channel

Multi mode viterbi decoder

LSI CORP

Timing error detector with diversity loop detector decision feedback

Systems and methods for multi-stage encoding of concatenated low density parity check codes

Automatic on-drive sync-mark search and threshold adjustment

Diversity loop detector with component detector switching

Ratio-adjustable sync mark detection system

Systems and methods for loop pulse estimation

ZENG LINGQI

Multiple interleavers in a coding system

Systematic encoding for non-full row rank, quasi-cyclic LDPC parity check matrices

Multistage LDPC encoding

Rate-scalable, multistage quasi-cyclic LDPC coding

LDPC decoding with on the fly error recovery

NG KIN MAN

LDPC selective decoding scheduling using a cost function

Implementation of LDPC selective decoding scheduling

LDPC selective decoding scheduling using a cost function

TANG XIANGYU

Buffer management in a turbo equalization system

Concatenated codes for recovering stored data

Adaptive scheduling of turbo equalization based on a metric

BROADLOGIC NETWORK TECH INC

Method and system for providing multi-channel multimode QAM equalization and carrier recovery

Fully parallel multi-channel demodulator

ETOPUS TECHNOLOGY INC

Receiver with adjustable reference voltages

Receiver for high speed communication channel

BELLORADO JASON

Adjusting receiver parameters without known data

LINK A MEDIA DEVICES CORP

Degree limited polynomial in Reed-Solomon decoding

CHAN KAI KEUNG

Data recovery using existing reconfigurable read channel hardware