Inventor

GOO JUNG-SUK

US34 patents

⚠️ This page may combine multiple inventors who share the name “GOO JUNG-SUK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOO JUNG-SUK

ADVANCED MICRO DEVICES INC

FinFET device incorporating strained silicon in the channel region

Method of fabricating an integrated circuit channel region

Formation of finFET using a sidewall epitaxial layer

Semiconductor device having a thick strained silicon layer and method of its formation

Method of growing as a channel region to reduce source/drain junction capacitance

Semiconductor on insulator MOSFET having strained silicon channel

Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift

Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication

Silicon on insulator substrate having improved thermal conductivity and method of its formation

Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Strained silicon semiconductor on insulator MOSFET

Replacement gate strained silicon finFET process

CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric

Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure

Strained silicon MOSFET having improved thermal conductivity and method for its fabrication

Strained silicon MOSFETs having improved thermal dissipation

Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication

Shallow trench isolation process and structure with minimized strained silicon consumption

Shallow trench isolation process using oxide deposition and anneal

Depletion to avoid cross contamination

Method for adjusting a transistor model for increased circuit simulation accuracy

Dynamic random access memory (DRAM) cells and methods for fabricating the same

GLOBALFOUNDRIES INC

Body tie test structure for accurate body effect measurement

Integrated circuit system with MOS device

Shallow trench isolation process and structure with minimized strained silicon consumption

Field effect transistor having increased carrier mobility

LG SEMICON CO LTD

Method for isolating elements in a semiconductor device

Method of fabricating a nonvolatile semiconductor memory device

TOPALOGLU RASIT O

Two-step simulation methodology for aging simulations

WASON VINEET

Method for robust statistical semiconductor device modeling

CHO HYUN-JIN

Dynamic random access memory (DRAM) cells and methods for fabricating the same

GOO JUNG-SUK

Method and apparatus for simulating gate capacitance of a tucked transistor device

MADHAVAN SRIRAM

Body tie test structure for accurate body effect measurement

CHEN QIANG

Silicon-on-insulator (“SOI”) transistor test structure for measuring body-effect