Inventor
ALTMAN ERIK R
US22 patents
⚠️ This page may combine multiple inventors who share the name “ALTMAN ERIK R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS6779049B2Aug 17, 2004
Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
IBM74 citations98
US10078571B2Sep 18, 2018
Rule-based adaptive monitoring of application performance
IBM31 citations93
US7735072B1Jun 8, 2010
Method and apparatus for profiling computer program execution
IBM34 citations92
US6970982B2Nov 29, 2005
Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions
IBM20 citations92
US7487330B2Feb 3, 2009
Method and apparatus for transferring control in a computer system with dynamic compilation capability
IBM19 citations84
US9823994B2Nov 21, 2017
Dynamically identifying performance anti-patterns
IBM6 citations83
US7356673B2Apr 8, 2008
System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form
IBM14 citations83
US7340588B2Mar 4, 2008
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
IBM5 citations73
US6907477B2Jun 14, 2005
Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors
IBM11 citations73
US10176022B2Jan 8, 2019
Dynamically adapting a test workload to accelerate the identification of performance issues
IBM6 citations72
US7966478B2Jun 21, 2011
Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers
IBM1 citations63
US7516310B2Apr 7, 2009
Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor
IBM5 citations63
US7461209B2Dec 2, 2008
Transient cache storage with discard function for disposable data
IBM6 citations63
US7401209B2Jul 15, 2008
Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction
IBM2 citations63
US7206923B2Apr 17, 2007
Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling
IBM3 citations63
US7865699B2Jan 4, 2011
Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
IBM2 citations62
US6704855B1Mar 9, 2004
Method and apparatus for reducing encoding needs and ports to shared resources in a processor
IBM3 citations62
US7971033B2Jun 28, 2011
Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class
IBM0 citations52
US10346283B2Jul 9, 2019
Dynamically identifying performance anti-patterns
IBM0 citations51
US7979682B2Jul 12, 2011
Method and system for preventing livelock due to competing updates of prediction information
IBM0 citations42