Inventor

WELLMAN JOHN-DAVID

US33 patents

⚠️ This page may combine multiple inventors who share the name “WELLMAN JOHN-DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WELLMAN JOHN-DAVID

IBM

Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism

Method and apparatus for memory prefetching based on intra-page usage history

Implementing instruction set architectures with non-contiguous register file specifiers

Implementing instruction set architectures with non-contiguous register file specifiers

System and method of execution of register pointer instructions ahead of instruction issues

Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions

Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching

Token based DMA

Single thread cache miss rate estimation

Non-homogeneous multi-processor system with shared memory

Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code

Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors

Heterogeneous system on a chip scheduler with learning agent

Transient cache storage with discard function for disposable data

Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling

System and method for instruction memory storage and processing based on backwards branch control information

Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code

Computer processing system employing an instruction schedule cache

System and method of execution of register pointer instructions ahead of instruction issue

Learning agent based application scheduling

Heterogeneous system on a chip scheduler

Instruction sequence merging and splitting for optimized accelerator implementation

Augmenting of automated clustering-based trace sampling methods by user-directed phase detection

Single-thread cache miss rate estimation

GSCHWIND MICHAEL KARL

Implementing instruction set architectures with non-contiguous register file specifiers

Implementing instruction set architectures with non-contiguous register file specifiers

Methods for generating code for an architecture encoding an extended register specification

Methods for generating code for an architecture encoding an extended register specification

Methods for generating code for an architecture encoding an extended register specification

BOSE PRADIP

Modeling system-level effects of soft errors

ALTMAN ERIK R

Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals

ALTMAN ERIK RICHTER

Control signal memoization in a multiple instruction issue microprocessor

EICHENBERGER ALEXANDRE E

Method and apparatus for data stream alignment support