Inventor
DAMBERG PHILIP
US39 patents
⚠️ This page may combine multiple inventors who share the name “DAMBERG PHILIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TESSERA INC
14 patentsUS6765288B2Jul 20, 2004
Microelectronic adaptors, assemblies and methods
TESSERA INC156 citations99
US7709968B2May 4, 2010
Micro pin grid array with pin motion isolation
TESSERA INC65 citations98
US7149095B2Dec 12, 2006
Stacked microelectronic assemblies
TESSERA INC65 citations97
US6885106B1Apr 26, 2005
Stacked microelectronic assemblies and methods of making same
TESSERA INC78 citations97
US7732912B2Jun 8, 2010
Semiconductor chip packages and assemblies with chip carrier units
TESSERA INC27 citations92
US7521785B2Apr 21, 2009
Packaged systems with MRAM
TESSERA INC23 citations92
US7061122B2Jun 13, 2006
Components, methods and assemblies for multi-chip packages
TESSERA INC44 citations92
US9318460B2Apr 19, 2016
Substrate and assembly thereof with dielectric removal for increased post height
TESSERA INC8 citations84
US9716075B2Jul 25, 2017
Semiconductor chip assembly and method for making same
TESSERA INC0 citations52
US9666450B2May 30, 2017
Substrate and assembly thereof with dielectric removal for increased post height
TESSERA INC0 citations52
US8981579B2Mar 17, 2015
Impedance controlled packages with metal sheet or 2-layer rdl
TESSERA INC0 citations52
US8816514B2Aug 26, 2014
Microelectronic assembly with joined bond elements having lowered inductance
TESSERA INC0 citations52
US9337165B2May 10, 2016
Method for manufacturing a fan-out WLP with package
TESSERA INC0 citations51
US6534392B1Mar 18, 2003
Methods of making microelectronic assemblies using bonding stage and bonding stage therefor
TESSERA INC0 citations50
INVENSAS CORP
7 patentsUS9041227B2May 26, 2015
Package-on-package assembly with wire bond vias
INVENSAS CORP37 citations97
US8940630B2Jan 27, 2015
Method of making wire bond vias and microelectronic package having wire bond vias
INVENSAS CORP48 citations94
US9761558B2Sep 12, 2017
Package-on-package assembly with wire bond vias
INVENSAS CORP4 citations84
US11189595B2Nov 30, 2021
Package-on-package assembly with wire bond vias
INVENSAS CORP0 citations62
US9252122B2Feb 2, 2016
Package-on-package assembly with wire bond vias
INVENSAS CORP2 citations62
US10756049B2Aug 25, 2020
Package-on-package assembly with wire bond vias
INVENSAS CORP0 citations52
US8951845B2Feb 10, 2015
Methods of fabricating a flip chip package for dram with two underfill materials
INVENSAS CORP1 citations52
CHAU ELLIS
3 patentsHABA BELGACEM
3 patentsUS8786083B2Jul 22, 2014
Impedance controlled packages with metal sheet or 2-layer RDL
HABA BELGACEM5 citations73
US8410618B2Apr 2, 2013
Microelectronic assembly with joined bond elements having lowered inductance
HABA BELGACEM3 citations63
US9136197B2Sep 15, 2015
Impedence controlled packages with metal sheet or 2-layer RDL
HABA BELGACEM0 citations42
SATO HIROAKI
3 patentsUS8957520B2Feb 17, 2015
Microelectronic assembly comprising dielectric structures with different young modulus and having reduced mechanical stresses between the device terminals and external contacts
SATO HIROAKI2 citations62
US8890304B2Nov 18, 2014
Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer material
SATO HIROAKI3 citations62
US8525338B2Sep 3, 2013
Chip with sintered connections to package
SATO HIROAKI1 citations51