Inventor

PEIDOUS IGOR V

US18 patents

⚠️ This page may combine multiple inventors who share the name “PEIDOUS IGOR V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PEIDOUS IGOR V

CHARTERED SEMICONDUCTOR MFG

Shallow trench isolation of MOSFETS with reduced corner parasitic currents

Method to form shallow trench isolation structures with improved isolation fill and surface planarity

Method of shallow trench isolation

Sub-quarter-micron MOSFET and method of its manufacturing

Method for making sub-quarter-micron MOSFET

Locos with bird&#39;s beak suppression by a nitrogen implantation

Narrow deep trench isolation process with trench filling by oxidation

LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect

Method and mask structure for self-aligning ion implanting to form various device structures

Method and mask structure for self-aligning ion implanting to form various device structures

Method and mask structure for self-aligning ion implanting to form various device structures

Method and mask structure for self-aligning ion implanting to form various device structures

Method and mask structure for self-aligning ion implanting to form various device structures

Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect

Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect

Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect

WARD MICHAEL G

Methods to adjust threshold voltage in semiconductor devices

Methods of forming a metal silicide region in an integrated circuit

Locos with bird's beak suppression by a nitrogen implantation