Inventor

SRIDHAR SEETHARAMAN

US71 patents

⚠️ This page may combine multiple inventors who share the name “SRIDHAR SEETHARAMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SRIDHAR SEETHARAMAN

TEXAS INSTRUMENTS INC

Multiple shielding trench gate fet

Dual RESURF trench field plate in vertical MOSFET

Integrated bipolar junction transistor for mixed signal circuits

Low resistance sinker contact

LDMOS CHC reliability

Lateral metal oxide semiconductor drain extension design

High performance PNP bipolar device fully compatible with CMOS process

Shallow trench isolation with conductive hard mask for in-line moat/trench width electrical measurements

Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process

Use of a single mask during the formation of a transistor&#39;s drain extension and recessed strained epi regions

Vertical trench gate MOSFET with integrated Schottky diode

Method to selectively recess ETCH regions on a wafer surface using capoly as a mask

High voltage lateral junction diode device

Vertical trench gate MOSFET with deep well region for junction termination

Semiconductor device having polysilicon field plate for power MOSFETs

Power transistor with terminal trenches in terminal resurf regions

Low resistance sinker contact

Integrated high-side driver for P-N bimodal power device

Reduced area power devices using deep trench isolation

Multiple shielding trench gate FET

Reduction of polysilicon residue in a trench for polysilicon trench filling processes

Application of different isolation schemes for logic and embedded memory

Application of different isolation schemes for logic and embedded memory

Application of different isolation schemes for logic and embedded memory

High voltage CMOS with triple gate oxide

Silicon epitaxy for high aspect ratio, substantially perpendicular deep silicon trench

High voltage CMOS with triple gate oxide

Multi-mode high voltage circuit

Resistor divider with improved resistor matching

Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom

Method to selectively strain NMOS devices using a cap poly layer

Trench shield isolation layer

Trench shield isolation layer

High-voltage drain expended MOS transistor

High-voltage drain extended MOS transistor

High voltage lateral junction diode device

Application of different isolation schemes for logic and embedded memory

Electrostatic discharge guard ring with snapback protection

Electrostatic discharge guard ring with complementary drain extended devices

Electrostatic discharge guard ring with snapback protection

Electrostatic discharge guard ring with complementary drain extended devices

ESD guard ring with snapback protection and lateral buried layers

Semiconductor devices with a sloped surface

Semiconductor device including a lateral insulator

Power transistor with terminal trenches in terminal resurf regions

SADRA KAYVAN

Application of different isolation schemes for logic and embedded memory

TEXAS INSTR INCORPATED

Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride

DENISON MARIE

Strained LDMOS and demos

SRIDHAR SEETHARAMAN

Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS process flow

CHATTERJEE AMITAVA

Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom

Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions