Inventor

HIBBELER JASON D

US59 patents

⚠️ This page may combine multiple inventors who share the name “HIBBELER JASON D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HIBBELER JASON D

IBM

Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs

Use of redundant routes to increase the yield and reliability of a VLSI layout

Technology migration for integrated circuits with radical design restrictions

Dynamic CPU usage profiling and function call tracing

Variable resistance switch for wide bandwidth resonant global clock distribution

Integrated circuit selective scaling

Technology migration for integrated circuits with radical design restrictions

Use of a layout-optimization tool to increase the yield and reliability of VLSI designs

Changing resonant clock modes

Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization

Tunable sector buffer for wide bandwidth resonant global clock distribution

Wide bandwidth resonant global clock distribution

Integrated circuit selective scaling

Technology migration for integrated circuits with radical design restrictions

Method, apparatus and computer program product for optimizing an integrated circuit layout

Test yield estimate for semiconductor products created from a library

Integrated circuit yield enhancement using Voronoi diagrams

Immunity to inline charging damage in circuit designs

Integrated circuit design layout optimizer based on process variation and failure mechanism

Technology migration for integrated circuits with radical design restrictions

Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic

Systematic yield in semiconductor manufacture

Optimizing integrated circuit designs based on interactions between multiple integration design rules

Setting switch size and transition pattern in a resonant clock distribution system

Setting switch size and transition pattern in a resonant clock distribution system

Setting switch size and transition pattern in a resonant clock distribution system

Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool

Context aware sub-circuit layout modification

Cloned and original circuit shape merging

Test yield estimate for semiconductor products created from a library

Layout optimization using parameterized cells

Systematic yield in semiconductor manufacture

Systematic yield in semiconductor manufacture

Content based yield prediction of VLSI designs

Independent migration of hierarchical designs with methods of finding and fixing opens during migration

Method for implementing overlay-based modification of VLSI design layout

Automated configuration of on-circuit facilities

Method for IC wiring yield optimization, including wire widening during and after routing

Tunable sector buffer for wide bandwidth resonant global clock distribution

Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique

Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design

COHN JOHN M

Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean

Method for IC wiring yield optimization, including wire widening during and after routing

BICKFORD JEANNE P

Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool

Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool

ANDERSON BRENT A

Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

ALLEN ROBERT J

Technology migration for integrated circuits with radical design restrictions

HIBBELER JASON D

Image sensor pixel structure employing a shared floating diffusion