Inventor
ONG YU YING
MY19 patents
⚠️ This page may combine multiple inventors who share the name “ONG YU YING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
8 patentsUS11580054B2Feb 14, 2023
Scalable network-on-chip for high-bandwidth memory
INTEL CORP2 citations71
US11164847B2Nov 2, 2021
Methods and apparatus for managing thermal behavior in multichip packages
INTEL CORP2 citations68
US12572500B2Mar 10, 2026
Scalable network-on-chip for high-bandwidth memory
INTEL CORP0 citations61
US11995028B2May 28, 2024
Scalable network-on-chip for high-bandwidth memory
INTEL CORP0 citations61
US11658159B2May 23, 2023
Methods and apparatus for managing thermal behavior in multichip packages
INTEL CORP0 citations58
US10714163B2Jul 14, 2020
Methods for mitigating transistor aging to improve timing margins for memory interface signals
INTEL CORP1 citations57
US11188255B2Nov 30, 2021
Dynamic major mode for efficient memory traffic control
INTEL CORP1 citations56
US12094551B2Sep 17, 2024
Modular error correction code circuitry
INTEL CORP0 citations43
SKYECHIP SDN BHD
7 patentsUS11609709B2Mar 21, 2023
Memory controller system and a method for memory scheduling of a storage device
SKYECHIP SDN BHD2 citations72
US12380056B2Aug 5, 2025
Network-on-chip system for optimizing data transfer
SKYECHIP SDN BHD0 citations51
US12199884B2Jan 14, 2025
Method and a system for network-on-chip arbitration
SKYECHIP SDN BHD0 citations48
US12210633B2Jan 28, 2025
Memory controller for improving data integrity and providing data security and a method of operating thereof
SKYECHIP SDN BHD0 citations47
US12393255B2Aug 19, 2025
System and a method for network-on-chip power management
SKYECHIP SDN BHD0 citations46
US11829643B2Nov 28, 2023
Memory controller system and a method of pre-scheduling memory transaction for a storage device
SKYECHIP SDN BHD0 citations46
US11575383B2Feb 7, 2023
Clocking system and a method of clock synchronization
SKYECHIP SDN BHD0 citations43
ALTERA CORP
3 patentsUS9342402B1May 17, 2016
Memory interface with hybrid error detection circuitry for modular designs
ALTERA CORP22 citations91
US9805775B1Oct 31, 2017
Integrated circuits with improved memory controllers
ALTERA CORP3 citations71
US9733855B1Aug 15, 2017
System and methods for adjusting memory command placement
ALTERA CORP5 citations69