Inventor

YAN CHUN

US48 patents

⚠️ This page may combine multiple inventors who share the name “YAN CHUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAN CHUN

APPLIED MATERIALS INC

Copper residue chamber clean

Method of pattern etching a low K dielectric layer

Method of etching patterned layers useful as masking during subsequent etching or for damascene structures

Method for etching low k dielectrics

Method of etching dielectric layers using a removable hardmask

Plasma assisted processing chamber with separate control of species density

Method for removal of metallic residue after plasma etching of a metal layer

Method and apparatus for asymmetric gas distribution in a semiconductor wafer processing system

System and method for etching organic anti-reflective coating from a substrate

Method and apparatus for providing uniform plasma in a magnetic field enhanced plasma reactor

Method for etching silicon oxynitride and dielectric antireflection coatings

Method for etching silicon oxynitride and dielectric antireflection coatings

Method for removing conductive residue

Methods for etching an organic anti-reflective coating

Method and apparatus for controlling the magnetic field intensity in a plasma enhanced semiconductor wafer processing chamber

Integrated system and method for source/drain engineering

Method for wafer outgassing control

Method of epitaxial growth shape control for CMOS applications

Method for conditioning a processing chamber for steady etching rate control

Method and apparatus for wafer outgassing control

Integrated method for wafer outgassing reduction

Method of forming structures with V shaped bottom on silicon substrate

Method and solution for cleaning InGaAs (or III-V) substrates

Method for removing native oxide and residue from a III-V group containing surface

Method of uniform channel formation

Method of utilizing a degassing chamber to reduce arsenic outgassing following deposition of arsenic-containing material on a substrate

Method for removing native oxide and residue from a III-V group containing surface

Self-aligned process for sub-10nm fin formation

Methods and solutions for cleaning INGAAS (or III-V) substrates

System and method in indium-gallium-arsenide channel height control for sub 7nm FinFET

Integrated system and method for source/drain engineering

Methods for removing contamination from surfaces in substrate processing systems

Silicon-containing substrate cleaning procedure

UV radiation system and method for arsenic outgassing control in sub 7nm CMOS fabrication

Integrated process and structure to form III-V channel for sub-7nm CMOS devices

Methods of surface interface engineering

MATTSON TECH INC

Ozone treatment for selective silicon nitride etch over silicon

Spacer etching process

Silicon mandrel etch after native oxide punch-through

Processing of workpieces using fluorocarbon plasma

Processing of workpieces using deposition process and etch process

Spacer open process by dual plasma

(unassigned)

Method of fabricating a magneto-resistive random access memory (MRAM) device

Method for planarizing a copper interconnect structure

IBM

Subtractive plasma etching of a blanket layer of metal or metal alloy

Sputter etch processing for heavy metal patterning in integrated circuits

LAM RES CORP

Methods for silicon electrode assembly etch rate and etch uniformity recovery

HANGZHOU HIKVISION DIGITAL TEC

Method for protecting cloud storage video data and system thereof