Inventor

SHIMANOUCHI MASASHI

US24 patents

⚠️ This page may combine multiple inventors who share the name “SHIMANOUCHI MASASHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIMANOUCHI MASASHI

INTEL CORP

Short link efficient interconnect circuitry

PAM-n jitter/noise decomposition analysis

Short link efficient interconnect circuitry

PAM-n jitter/noise decomposition analysis

Techniques for generating a PAM eye diagram in a receiver

Short link efficient interconnect circuitry

Decomposable forward error correction

Systems and methods for supporting both pulse amplitude modulation and quadrature amplitude modulation

ALTERA CORP

Methods for joint optimization of link equalization

Simulation tool for high-speed communications links

Methods for built-in self-measurement of jitter for link components

Methods and apparatus for accurate transmitter simulation for link optimization

Communication link control using communication interface and programmable logic circuitry

Method and apparatus for processing data and performing crosstalk simulation

Techniques for monitoring and control of high speed serial communication link

CREDENCE SYSTEMS CORP

Method and system for improved ATE timing calibration at a device under test

Method and apparatus for high speed IC test interface

Loadboard enhancements for automated test equipment

LI PENG

Simulation tool for high-speed communications links

Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

DING WEIQI

On-die jitter generator

Bit error rate checker receiving serial data signal from an eye viewer

PAN MINGDE

Multi-level amplitude signaling receiver

SHIMANOUCHI MASASHI

Methods and apparatus for generating short length patterns that induce inter-symbol interference