Inventor

KALNITSKY ALEXANDER

US271 patents

⚠️ This page may combine multiple inventors who share the name “KALNITSKY ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KALNITSKY ALEXANDER

NAT SEMICONDUCTOR CORP

EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming

Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure

Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages

Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors

Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages

Single-poly EPROM cell with CMOS compatible programming voltages

EPROM and flash memory cells with source-side injection

Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology

Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology

CMOS compatible pixel cell that utilizes a gated diode to reset the cell

CMOS compatible pixel cell that utilizes a gated diode to reset the cell

Methods of fabricating floating gate semiconductor device with reduced erase voltage

Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture

Single-poly EPROM cell with CMOS compatible programming voltages

Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture

Floating gate semiconductor device with reduced erase voltage

Method of fabricating a high density EEPROM array

Polysilicon fuse that provides an open current path when programmed without exposing the fuse to the environment

Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data

Memory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasure

Memory cell having an erasable Frohmann-Bentchkowsky memory transistor

Sense amplifier having a bias circuit with a reduced size

Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors

Antifuse with a silicide layer overlying a diffusion region

Method for forming EPROM and flash memory cells with source-side injection

I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection

Electrostatic discharge protection device

SGS THOMSON MICROELECTRONICS

Volatile memory cell with interface charge traps

Method of making volatile memory cell with interface charge traps

Method of via formation for the multilevel interconnect integrated circuits

Integrated overvoltage protection device having electrodes separated by a gas-filled cavity

Method of forming a polysilicon buried contact

Radiation hard integrated circuits with implanted silicon in gate oxide layer, field oxide region, and interlevel dielectric layer

ST MICROELECTRONICS INC

Electrostatic discharge protection of a capacitve type fingerprint sensing array

Solid state fingerprint sensor packaging apparatus and method

Semiconductor variable capacitor

Solid state optical imaging pixel with resistive load

Method of making a semiconductor variable capacitor

TAIWAN SEMICONDUCTOR MFG CO LTD

High voltage integration for HKMG technology

Sensor device, image sensor array and manufacturing method of sensor device

Semiconductor structure and manufacturing method thereof

MAXIM INTEGRATED PRODUCTS

Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates

Bipolar transistor and methods of forming bipolar transistors

Method of forming self-aligned bipolar transistor

UPEK INC

Electrostatic discharge protection of a capacitive type fingerprint sensing array

Electrostatic discharge protection of a capacitive type fingerprint sensing array

KALNITSKY ALEXANDER

CMOS compatible BioFET

Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide

INTERSIL INC

Memory array of floating gate-based non-volatile memory cells

Flash memory array of floating gate-based non-volatile memory cells