Inventor

HAVLIR ANDREW M

US36 patents

⚠️ This page may combine multiple inventors who share the name “HAVLIR ANDREW M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAVLIR ANDREW M

APPLE INC

Dependency handling for set-aside of compute control stream commands

Distributed compute work parser circuitry using communications fabric

Operand cache control techniques

Operand cache flush, eviction, and clean techniques using hint information and dirty information

Intelligent caching for an operand cache

Operand cache design

Apparatus implementing instructions that impose pipeline interdependencies

Techniques for context switching using distributed compute workload parsers

Fast determination of workgroup batches from multi-dimensional kernels

Pipelined allocation for operand cache

Floating-point multiply-add with down-conversion

Hint values for use with an operand cache

Logical slot to hardware slot mapping for graphics processors

Distributing compute work using distributed parser circuitry

Low latency fetch circuitry for compute kernels

Instruction storage

Instruction storage

Techniques for discarding graphics work for quality of service

Unified integer and floating-point compare circuitry

Multi-threaded GPU pipeline

Low latency fetch circuitry for compute kernels

Dynamic buffering control for compute work distribution

Dependency scheduling for control stream in parallel processor

GPU instruction storage

Queuing system for register file access

GPU predication

Affinity-based graphics scheduling

Software control techniques for graphics hardware that supports logical slots and reservation of graphics hardware based on a priority threshold

Compute kernel parsing with limits in one or more dimensions with iterating through workgroups in the one or more dimensions for execution

Completion signaling techniques in distributed processor

Operand cache coherence for SIMD processor supporting predication

Clock routing techniques

Clause chaining for clause-based instruction execution

Re-using graphics vertex identifiers for primitive blocks across states

High-speed low-power access to register files

SENINGEN MICHAEL R

Bit slice elements utilizing through device routing