P

Inventor

ARORA PUNEET

IN28 patents
⚠️ This page may combine multiple inventors who share the name “ARORA PUNEET”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CADENCE DESIGN SYSTEMS INC

18 patents
US9865362B1Jan 9, 2018

Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)

CADENCE DESIGN SYSTEMS INC9 citations82
US9640280B1May 2, 2017

Power domain aware insertion methods and designs for testing and repairing memory

CADENCE DESIGN SYSTEMS INC8 citations82
US10783299B1Sep 22, 2020

Simulation event reduction and power control during MBIST through clock tree management

CADENCE DESIGN SYSTEMS INC2 citations72
US10387599B1Aug 20, 2019

Systems, methods, and computer-readable media utilizing improved data structures and design flow for programmable memory built-in self-test (PMBIST)

CADENCE DESIGN SYSTEMS INC2 citations72
US10319459B1Jun 11, 2019

Customizable built-in self-test testplans for memory units

CADENCE DESIGN SYSTEMS INC2 citations72
US10095822B1Oct 9, 2018

Memory built-in self-test logic in an integrated circuit design

CADENCE DESIGN SYSTEMS INC4 citations71
US10192013B1Jan 29, 2019

Test logic at register transfer level in an integrated circuit design

CADENCE DESIGN SYSTEMS INC5 citations69
US10593419B1Mar 17, 2020

Failing read count diagnostics for memory built-in self-test

CADENCE DESIGN SYSTEMS INC1 citations61
US12307186B1May 20, 2025

Launch off shift process

CADENCE DESIGN SYSTEMS INC0 citations60
US12007440B1Jun 11, 2024

Systems and methods for scan chain stitching

CADENCE DESIGN SYSTEMS INC1 citations58
US11971818B1Apr 30, 2024

Memory view for non-volatile memory module

CADENCE DESIGN SYSTEMS INC0 citations51
US11966633B1Apr 23, 2024

Control algorithm generator for non-volatile memory module

CADENCE DESIGN SYSTEMS INC0 citations51
US10504607B1Dec 10, 2019

Multiple-channel, programmable fuse control unit

CADENCE DESIGN SYSTEMS INC0 citations51
US10482989B1Nov 19, 2019

Dynamic diagnostics analysis for memory built-in self-test

CADENCE DESIGN SYSTEMS INC0 citations51
US10395747B1Aug 27, 2019

Register-transfer level design engineering change order strategy

CADENCE DESIGN SYSTEMS INC0 citations51
US10007489B1Jun 26, 2018

Automated method identifying physical memories within a core or macro integrated circuit design

CADENCE DESIGN SYSTEMS INC1 citations51
US12417029B1Sep 16, 2025

Memory view for memory module

CADENCE DESIGN SYSTEMS INC0 citations47
US12393246B1Aug 19, 2025

Power consumption estimation of memory under test

CADENCE DESIGN SYSTEMS INC0 citations41

ARORA PUNEET

3 patents

MICROSOFT TECHNOLOGY LICENSING LLC

2 patents

ATLASSIAN PTY LTD

1 patent

CHAKRAVADHANULA KRISHNA

1 patent

GREGOR STEVEN LEE

1 patent

CARD NORMAN

1 patent

EMC IP HOLDING CO LLC

1 patent