Inventor
KAUSHIK NAVNEET
IN6 patents
⚠️ This page may combine multiple inventors who share the name “KAUSHIK NAVNEET”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
4 patentsUS9865362B1Jan 9, 2018
Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)
CADENCE DESIGN SYSTEMS INC9 citations82
US9640280B1May 2, 2017
Power domain aware insertion methods and designs for testing and repairing memory
CADENCE DESIGN SYSTEMS INC8 citations82
US10095822B1Oct 9, 2018
Memory built-in self-test logic in an integrated circuit design
CADENCE DESIGN SYSTEMS INC4 citations71
US10192013B1Jan 29, 2019
Test logic at register transfer level in an integrated circuit design
CADENCE DESIGN SYSTEMS INC5 citations69