Inventor
NESTORK WILLIAM J
US4 patents
Patents
4 patentsUS3954523AMay 4, 1976
Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
IBM60 citations95
US5160987ANov 3, 1992
Three-dimensional semiconductor structures formed from planar layers
IBM197 citations94
US4602271AJul 22, 1986
Personalizable masterslice substrate for semiconductor chips
IBM60 citations92
US4899208AFeb 6, 1990
Power distribution for full wafer package
IBM10 citations65