Inventor

GABOR RON

IL63 patents

⚠️ This page may combine multiple inventors who share the name “GABOR RON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GABOR RON

INTEL CORP

Hardware apparatuses and methods for memory corruption detection

Memory corruption detection

Multiple chunk support for memory corruption detection architectures

Memory write protection for memory corruption detection architectures

Power aware software pipelining for hardware accelerators

Real-time threading service for partitioned multiprocessor systems

Multiple, cooperating operating systems (OS) platform system and method

64-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s)

Hardware apparatuses and methods for memory corruption detection

Memory protection with hidden inline metadata

Linear memory address transformation and management

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Heap management for memory corruption detection

Byte level granularity buffer overflow detection for memory corruption detection architectures

Heap management for memory corruption detection

Performing local power gating in a processor

Advanced error detection for integer single instruction, multiple data (SIMD) arithmetic operations

End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures

Memory protection with hidden inline metadata

Memory protection with hidden inline metadata

Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Enhanced address space layout randomization

Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

Enhanced address space layout randomization

Memory write protection for memory corruption detection architectures

Byte level granularity buffer overflow detection for memory corruption detection architectures

Performing local power gating in a processor

Restricted speculative execution mode to prevent observable side effects

Posting weakly ordered transactions

Performance simulation of multiprocessor systems

System, apparatus and method for multi-cacheline small object memory tagging

Hardware apparatuses and methods for memory corruption detection

Hardware apparatuses and methods to check data storage devices for transient faults

Interfacing with block-based storage in a processor

Recovery from multiple data errors

Hardware apparatuses and methods to check data storage devices for transient faults

Device, system and method to detect an uninitialized memory read

Server RAS leveraging multi-key encryption

RAPPOPORT LIHU

Efficient method and apparatus for employing a micro-op cache in a processor

Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor

Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

GABOR RON

Acceleration threads on idle OS-visible thread execution units

Code reuse and locality hinting

SAGER DAVID J

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

BONEN NADAV

Performing local power gating in a processor

OUZIEL IDO

System and method for fusing instructions queued during a time window defined by a delay counter

SPERBER ZEEV

Recoverable parity and residue error

FALIK OHAD

Optimizing performance of instructions based on sequence detection or information associated with the instructions