Inventor

GONION JEFFRY E

US111 patents

⚠️ This page may combine multiple inventors who share the name “GONION JEFFRY E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GONION JEFFRY E

APPLE INC

Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture

Macroscalar processor architecture

Macroscalar processor architecture

Macroscalar processor architecture

Return-oriented programming (ROP)/jump oriented programming (JOP) attack protection

Copy-propagate, propagate-post, and propagate-prior instructions for processing vectors

Running-shift instructions for processing vectors using a base value from a key element of an input vector

Shift-in-right instructions for processing vectors

Generating predicate values during vector processing

Macroscalar processor architecture

Instructions for efficiently accessing unaligned partial vectors

Instructions for efficiently accessing unaligned vectors

Memory controller mapping on-the-fly

Running-AND, running-OR, running-XOR, and running-multiply instructions for processing vectors using a base value from a key element of an input vector

Running-sum instructions for processing vectors using a base value from a key element of an input vector

Break, pre-break, and remaining instructions for processing vectors

Cryptographic signatures for capability-based addressing

Computation engine that operates in matrix and vector modes

Systems and methods for performing memory compression

Auto multi-threading in macroscalar compilers

Processing vectors using wrapping multiply and divide instructions in the macroscalar architecture

Memory-hazard detection and avoidance instructions for vector processing

Method and apparatus for compressing and decompressing data

Matrix computation engine

Memory controller mapping on-the-fly

GONION JEFFRY E

Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector

Macroscalar processor architecture

Check-hazard instructions for processing vectors

Technique for visually compositing a group of graphical objects

Vector index instruction for generating a result vector with incremental values based on a start value and an increment value

Non-faulting and first-faulting instructions for processing vectors

Detecting memory-hazard conflicts during vector processing

Predicate count and segment count instructions for processing vectors

Predicting a result of a dependency-checking instruction when processing vector instructions

Predicting a result for an actual instruction when processing vector instructions

Generating predicate values based on conditional data dependency in vector processors

Systems and methods for compiler-based vectorization of non-leaf code

Macroscalar processor architecture

Using addresses to detect overlapping memory regions

Processing vectors using wrapping add and subtract instructions in the macroscalar architecture

Instruction for comparing active vector elements to preceding active elements to determine value differences

Running multiply-accumulate instructions for processing vectors

Running unary operation instructions for processing vectors

Running subtract and running divide instructions for processing vectors

Memory-hazard detection and avoidance instructions for vector processing

Conditional data-dependency resolution in vector processors

Generating stop indicators based on conditional data dependency in vector processors

Macroscalar processor architecture

Generating stop indicators during vector processing

SHENG GEORGE S

Digital signal processor using a reconfigurable array of macrocells